tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 7

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

Advance Data Sheet, Rev. 2
July 2001
Features
CDR Features
Agere Systems Inc.
DataLink (DS1-ESF DL) and SSM (E1 multiframe
Sa) fields read/writable.
Supports all Ultramapper modes of operation.
Complies with T1.107, T1.231, T1.403, G.703,
G.704, O.150.
Receives data at OC-12/STS-12 (622.08 Mbits/s)
data rate.
Single low-voltage power supply.
155.52 MHz or 77.76 MHz input reference clock for
on-chip PLL.
On-chip PLL for clock synthesis, requiring only one
external resistor, generating 16 phases, providing
resolution of ~100 ps.
PLL bypass mode for functional test.
Modular design to incorporate n = 2 to 16 channels.
Meets type B jitter tolerance specification of ITU-T
Recommendation G.958.
No output clock drift in absence of data transitions
once lock is acquired.
Built-in test features.
(continued)
TMXF84622 155 Mbits/s/622 Mbits/s Interface
System Test and Maintenance
Microprocessor Interface
Chip Testing and Maintenance
Interface to Other Agere Devices
Seamless interface to the following Agere Systems
devices:
* IEEE is a registered trademark of the Institute of Electrical and
Electronics Engineers, Inc
A variety of loopback modes implemented on
SONET/SDH side as well as on framer level.
Built-in test pattern generator and monitor config-
urable for simultaneously testing E1, DS1, DS2, E3,
DS3, and STS1 (one channel each).
21-bit address and 16-bit data interface with 16 MHz
to 66 MHz read and write access.
Compatible with most industry-standard processors.
IEEE * 1149.1 JTAG boundary scan.
TADM042G5
Super Mapper
SONET/SDH x84/x63 Ultramapper
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