tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 40

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information
Table 1. Pin Descriptions (continued)
* O
40
40
K1, L3, M5, J1
I/O
I
I
D
U
N2, P5, M1,
K2, M6, L5,
G1, L6, H2,
R6, N1, P3,
P6, M2, L1,
M3, N6, L2,
H3, K6, F1,
E1, F2, H5,
1
H1, J2, J3,
J5, J6, G2,
D1, F3, E2
; I/O
indicates internal pull-up.
2
indicates external pull-up recommended (unused or system required),
R5, P2
indicates external pull-down recommended (unused or system required),
D
Pin
P1
R3
R2
T6
indicate internal pull-down,
ADDR[20:0]
DATA[15:0]
APS_INTN
HP_INTN
LP_INTN
PAR[1:0]
Symbol
DTN
(continued)
Type
—
—
—
—
—
—
—
Microprocessor Interface (continued) (49)
Open
Drain
Open
Drain
Open
Drain
Open
Drain
I/O*
I/O
I/O
O
O
O
O
I
1
1
1
1
21-Bit Address Bus, for 16-Bit Data Bus. The address bus sig-
nals are latched transparently when ADSN is low.
ADDR20—MSB.
ADDR0—LSB.
Note: The Ultramapper is little-endian, the least significant byte is
16-Bit Data Bus. Device inputs for write operation and outputs for
read operation.
DATA15—MSB.
DATA0—LSB.
Data Parity. Byte-wide parity bits for data. PAR[1] is the parity for
DATA[15:8] and PAR[0] is the parity for DATA[7:0].
Data Transfer Acknowledge. In synchronous microprocessor
mode, the delay associated with DTN going low depends on the
Ultramapper block being accessed, the address within that block,
and the operating mode. In asynchronous microprocessor mode,
after qualification of ADSN and DSN by TLSC52 clock, DTN going
low depends on the Ultramapper block being accessed, the
address within that block, and the operating mode. Under all con-
ditions the user should wait until DTN is asserted before starting
the next operation. DTN goes high along with the rising edge of
ADSN.
Ultramapper High Priority Interrupt Request (Active-Low).
Ultramapper Low Priority Interrupt Request (Active-Low).
Automatic Protection Switch (APS) Interrupt Request
(Active-Low).
stored in the lowest address and the most significant byte is
stored in the highest address. Care must be exercised in
connection to microprocessors that use big-endian byte
ordering.
Description
Advance Data Sheet, Rev. 2
Agere Systems Inc.
July 2001