tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 26

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
2 The SONET/SDH Ultramapper
2.21 Signaling Processor
The signaling processor supports the following modes:
Signaling features supported per channel are as follows:
In the DS1 robbed-bit signaling modes and voice and data channels are programmable. The entire payload can be
forced into a data-only (no signaling channels) mode, i.e., transparent mode by programming one control bit.
Signaling access can be through the on-chip signaling registers or the system interface. Data and its associated
signaling information can be accessed through the system in either DS1 or CEPT-E1 modes.
2.22 Facility Data Link (FDL) Processor
The bit-oriented ESF data-link messages defined in ANSI T1.403 are monitored by the receive facility data link unit.
The transmit facility data link unit overrides the FDL-FIFO for the transmission of the bit-oriented ESF data-link
messages defined in ANSI T1.403-1995.
The FDL processor extracts and stores data link bits from three different frame types as follows:
The respective bits will always be extracted from frame-aligned frames and stored in a stack. The processor will
have control of being alerted to stack updates through the interrupt mask registers.
The transmit FDL block performs the transmission of D bits into SLC -96 Ultraframes, Sa-bits in CEPT frames, and
D bits in DDS frames.
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Ultraframe (D4, SLC-96): 2-state, 4-state, and 16-state.
VT 1.5 SPE: 2-state, 4-state, and 16-state.
Extended Ultraframe: 2-state, 4-state, and 16-state.
CEPT: common channel signaling (CCS) (TS-16).
Transparent (pass through) signaling.
J-ESF handling groups.
Signaling debounce.
Signaling freeze.
Signaling interrupt upon change of state.
Associated signaling mode (ASM).
Signaling inhibit.
Signaling stomp.
D bits and delineator bits from the SLC -96 multi-Ultraframe.
Data link bits from DDS frames (bit 6 of time-slot 24).
Two multiframes of Sa[4:8] bits from time slot 0 in CEPT basic and CRC-4 multiframes.
In SLC -96 frames, the D and delineator-bits are always sourced from this block when the block is enabled for
insertion.
In DDS frames, the data link bits are always sourced from this block when this block is enabled for insertion. This
block also provides the capability to transmit BOMs in the data link channel of ESF links.
In CEPT frames, the Sa-bits are sourced from either the Sa stack within this block or from the system interface.
The data link block only responds with valid data when selected by the Sa source control bits.
(continued)
Advance Data Sheet, Rev. 2
Agere Systems Inc.
July 2001