tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 30

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
3 Pin Information
Table 1. Pin Descriptions (continued)
* O
30
30
AN17, AN15,
AN18, AN16,
AP17, AP15,
AP18, AP16,
I/O
I
I
D
U
1
; I/O
indicates internal pull-up.
2
indicates external pull-up recommended (unused or system required),
AN13
AN14
AP13
AP14
AK15
AL14
AJ13
indicates external pull-down recommended (unused or system required),
AP3
AK6
AK8
AK9
AJ8
AJ6
AJ9
Pin
D
indicate internal pull-down,
RLSDATAN[3:1]
RLSDATAP[3:1]
TLSDATAN[3:1]
TLSDATAP[3:1]
RLSCLK
CTAPRH
CTAPTH
CTAPRP
TLSCLK
CTAPTL
Symbol
RESLO
RESHI
REF10
REF14
(continued)
LVDS
LVDS
Type
—
—
—
—
—
—
—
—
—
—
STS3/STM1 Mate Interconnect (14)
TMUX Block (continued)
LVDS Control Pins (8)
I/O*
—
—
—
—
O
O
O
I
I
I
I
I
155 Mbit/s STS-3/STM-1 Output Data. LVDS output.
155 Mbit/s STS-3/STM-1 Input Data. Input for clock and
Data Recovery (CDR). LVDS input.
19.44 MHz Receive Side Byte CLK.
19.44 MHz Transmit Side Byte CLK.
External 100
Note: A 100 W 1% resistor is required between RESHI and
External 100
External 1 V Reference Voltage Pin.
External 1.4 V Reference Voltage Pin.
LVDS Buffer Terminator Center Tap for RHSDP/N and
RHSCP/N. Optional, 0.1 µF capacitor connected between
CTAP pin and ground, to improve the common mode rejec-
tion of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for THSCP/N and
THSSYNNP/N. Optional, 0.1 µF capacitor connected
between CTAP pin and ground, to improve the common
mode rejection of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for RPSDP/N and
RPSCP/N. Optional, 0.1 µF capacitor connected between
CTAP pin and ground, to improve the common mode rejec-
tion of the LVDS input buffers.
LVDS Buffer Terminator Center Tap for TLSDATAP/N.
Optional, 0.1 µF capacitor connected between CTAP pin and
ground, to improve the common mode rejection of the LVDS
input buffers.
RESLO pins as a reference for the LVDS input buffer
termination.
Resistor Pin 1.
Resistor Pin 2. See note in RESHI pin.
Description
Advance Data Sheet, Rev. 2
Agere Systems Inc.
July 2001