tmxf84622 ETC-unknow, tmxf84622 Datasheet - Page 4

• Manufacturer Part Number: tmxf84622
• Description: Tmxf84622 Mbits/s/622 Mbits/s Interface Sonet/sdh X84/x63 Ultramapper
• Manufacturer: ETC-unknow

TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Features
MPU Features
4 4
— Maximum channel data rate: 64 kbits/s.
— Minimum channel data rate: 4 kbits/s (DS1-FDL or
— 128-byte FIFO per channel in both transmit and
— Tx to Rx loopback supported.
System interfaces:
— Concentration highway interface.
— Single clock and frame synchronizing signals;
— Parallel system bus interface at 19.44 MHz for
— Time-division multiplex data rate serial interface at
— Network serial multiplexed interface
21-bit address/16-bit data bus microprocessor inter-
face.
Synchronous (16 MHz to 66 MHz)/asynchronous
microprocessor interface modes.
Microprocessor data bus parity monitoring.
Summary of 2 level priority interrupts from major
functional blocks/maskable.
Separate device interrupt outputs for automatic pro-
tection switch and the Ultramapper global interrupt.
Global configuration of network performance moni-
toring counters operation.
Global software resets.
Global enabling and powering down of major func-
tional blocks.
Miscellaneous global configuration and control.
E1 Sa-bit).
receive direction.
programmable clock rates at 2.048 MHz,
4.096 MHz, 8.192 MHz, and 16.384 MHz;
programmable data rates at 2.048 Mbits/s,
4.096 Mbits/s, and 8.192 Mbits/s;
programmable clock edges and bit/byte offsets.
data and signaling: single clock and frame syn-
chronizing signals.
1.544 MHz or 2.048 MHz. Twenty-eight receive
data, clock, and frame synchronizing signals.
Twenty-eight transmit data signals with a global
clock and frame synchronization.
mal pin count serial interface at 51.84 MHz opti-
mized for data and IMA applications.
(continued)
(NSMI)
mini-
SPEMPR Features
The SPE mapper accepts/delivers TUG-2 data from/
to the VT mapper. The TUG-2 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers DS3 data from/to
the M13 MUX/deMUX. The DS3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers a clear DS3 signal
at 44.736 Mbits/s rate. The clear DS3 signal is
mapped/demapped essentially the same way as
M13 signal described above.
The SPE mapper accepts/delivers E3 data from/to
the E13 MUX/deMUX. The E3 data is mapped/
demapped either to/from an AU-3/STS-1 signal for
the North American digital systems or to/from a
TUG-3 signal for the ITU-based systems.
The SPE mapper accepts/delivers a clear E3 signal
at 34.368 Mbits/s rate. The clear E3 signal is
mapped/demapped essentially the same way as E13
signal described above.
The SPE mapper has a DS3/E3 loopback circuit
placed for the functions of demapping and remap-
ping a DS3/E3 signal. It is particularly useful in cases
where a DS3/E3 signal mapped as an AU-3/STS-1
signal has to be remapped as a TUG-3 signal or vice
versa.
The SPE mapper supports a path overhead access
channel more commonly known as the POAC chan-
nel. Seven path overhead bytes namely J1, C2, F2,
H4, F3, K3, and N1 may be inserted/dropped
through this channel. This channel works as the
master, which means that this channel provides a
clock in both transmit and receive directions and
POH data may be inserted by the user on the trans-
mit side or dropped by the block in the receive side.
Path overhead byte B3 (BIP error) generation/detec-
tion and programmable BIP-8 bit error rate insertion.
Programmable clear on read/clear on write registers.
Signal fail and signal degrade indicators available to
report bit error rates above a certain programmable
threshold.
Advance Data Sheet, Rev. 2
Agere Systems Inc.
July 2001