cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 110
cx28348
Manufacturer Part Number
cx28348
Description
Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28348.pdf
(195 pages)
- Current page: 110 of 195
- Download datasheet (2Mb)
Functional Description
2.4.4
2-64
Source Loopback
in loopback). Idle pattern and RAI transmission due to TxAlm bits are also valid
during this loopback.
When TxLOS bit in Feature2 Control register is set, an all-0s signal is output on the
transmitter and overrides the content of the frame looped from the receiver.
This loopback is activated by setting PayldLp bit in the Feature3 Control register.
The source loopback loops the transmitter encoder outputs back to the system through
the receiver decoder inputs. The receiver dejitter FIFO is meaningless in this mode,
since there is only one clock looped back from the transmitter circuit, TCLKO clock.
The transmitter data path is not affected by activation of this loopback and the
transmitted data is still present on TXPOS and TXNEG pins. The transmitted frame
can be overwritten by an AIS pattern by setting TxAlm bits in Mode Control register
to AIS control state. Doing this affects only TXPOS and TXNEG and not the looped
frame. Therefore, there is no way to generate an AIS pattern on the looped frame by
the transmitter. The same behavior applies to TxLOS bit. I.e., when TxLOS is set
during source loopback only TXPOS and TXNEG are forced to zero, the looped
frame is unaffected. When an AIS or LOS pattern is generated error insertion is
invalid. Idle pattern and RAI are not supported in this mode like AIS; i.e., they can
overwrite the looped frame by setting TxAlm bits as in normal operation.
Setting SourceLp bit in the Mode Control register activates this loopback.
NOTE:
NOTE:
Mindspeed Technologies™
The transmitter does not generate an AIS or Idle pattern independently due to AIS or
Idle detection in the receiver during this loopback. The microprocessor must
program the transmitter to generate an AIS/Idle according to the receiver detection.
The shallow line loopback and source loopback cannot be operated simultaneously.
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
Related parts for cx28348
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Framer SDH ATM/POS/STM-1 SONET/STS-3 3.3V 272-Pin BGA
Manufacturer:
Mindspeed Technologies
Part Number:
Description:
RS8234EBGC ATM XBR SAR
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
ATM SAR 155Mbps 3.3V ABR/CBR/GFR/UBR/VBR 388-Pin BGA
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
ATM IMA 8.192Mbps 1.8V/3.3V 484-Pin BGA
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
RS8234EBGD ATM XBR SAR, ROHS
Manufacturer:
Mindspeed Technologies
Part Number:
Description:
3-PORT T3/E3/STS-1 LIU WITH/ DJAT IC (ROHS)
Manufacturer:
Mindspeed Technologies
Part Number:
Description:
ATM IMA 800Mbps 1.8V/3.3V 256-Pin BGA
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Framer SDH ATM/POS/STM-1 SONET/STS-3 3.3V 272-Pin BGA
Manufacturer:
Mindspeed Technologies
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet:
Part Number:
Description:
Manufacturer:
Mindspeed Technologies
Datasheet: