cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 44
cx28348
Manufacturer Part Number
cx28348
Description
Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28348.pdf
(195 pages)
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Product Description
Table 1-16. Microprocessor Interface (2 of 2)
1-34
ALE
CS[A]*
CS[B]*
DTACK*
INTR[A]*
INTR[B]*
RW* (WR*)
DS* (RD*)
Pin Label
CX28346 Pin # CX28348 Pin #
H13
U12
T10
G14
T11
U11
N8
P7
Mindspeed Technologies™
U12
H13
G14
U11
T10
T11
N8
P7
O/Z
O/Z
O/Z
I/O
I
I
I
I
I
Address Strobe
Chip Select
Data Transfer
Acknowledge
Interrupt Request
Read/Write Direction
Data Strobe or Read
or Write Strobe
Signal Name
Strobe
For Intel bus mode only, ALE falling
edge asynchronously latches
address from A[8:0] (Motorola) or
A[8]+AD[7:0] (Intel) to identify one
register for subsequent read/write
data transfer cycle.
Active low enables read/write
decoder. Active high ends current
read or write cycle and places data
bus output in high impedance.
Open drain active low output
signifies in-progress data transfer
cycle. Data ready indication for
read, transaction end indication for
write
Open drain active low output
signifies one or more pending
interrupt requests. INTR goes to
high impedance state.
Active low write data strobe (WR*)
for MOTO* = 1, or data select (R/
W*) for MOTO* = 0.
Active low read data strobe (RD*)
for MOTO* = 1, or data strobe
(DS*) for MOTO* = 0.
CX28342/3/4/6/8 Data Sheet
Definition
28348-DSH-001-B
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