cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 170
cx28348
Manufacturer Part Number
cx28348
Description
Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28348.pdf
(195 pages)
- Current page: 170 of 195
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Electrical and Mechanical Specifications
Table 4-8. Intel Asynchronous Write Cycle (MOTO* = 1)
Figure 4-9. Motorola Asynchronous Read Cycle (MOTO* = 0)
4-10
FOOTNOTE:
(1)
(2)
DTACK*
Symbol
AD[7:0]
Clk is the cycle (ns) of the slowest clock (DS3—22 ns, E3–29 ns, HSSI—19 ns).
CS* can be kept low if only CX28342/CX28343/CX28344/CX28346/CX28348 device is in the system, otherwise any negative
edge of RD* or positive edge of WR* starts a read/write cycle.
A[8:0]
R/W*
10
11
12
1
2
3
4
5
6
7
8
9
CS*
DS*
ALE high pulse width
A[8], AD[7:0] Address setup to ALE low
A[8], AD[7:0] Address hold after ALE low
RD* high to CS* low
CS* low to WR* low
WR* high to CS* high
CS* high to RD* low
WR* pulse width low
AD[7:0] input data setup to WR* high
AD[7:0] input data hold after WR* high
WR* high to next WR* low or RD* low
ALE low to WR* low
Parameter
Address
1
Mindspeed Technologies™
3
6
5
3 x clk + 15 (1)
Minimum
15
15
5
5
3
3
3
3
5
5
5
Read Data
Maximum
9
CX28342/3/4/6/8 Data Sheet
7
4
—
—
—
—
—
—
—
—
—
—
—
—
4
2
8
28348-DSH-001-B
Units
100542_030
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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