cx28348 Mindspeed Technologies, cx28348 Datasheet - Page 78
cx28348
Manufacturer Part Number
cx28348
Description
Dual/triple/quad/hex/octal-enhanced Ds3/e3 Framer
Manufacturer
Mindspeed Technologies
Datasheet
1.CX28348.pdf
(195 pages)
- Current page: 78 of 195
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Functional Description
2.1.5.2
Table 2-5. Setting the Error Insertion1 Control Register in E3-G.751 Mode
2-32
Error
FAS
RAI
FrmErrF
YelErr
Bit
Table 2-4. Setting the Error Insertion1 Control Register in DS3 Mode (2 of 2)
E3-G.751 Mode
In the E3-G.751 mode of operation, setting bits at the Error Insertion1 Control register
can generate the errors listed in
FEBE
FOOTNOTE:
(1)
(2)
In DS3 C-bit parity mode.
Active in C-bit parity only.
(2)
Error
Set to
Mindspeed Technologies™
1
1
FEBEErr
Bit
Causes one bit of the next FAS sequence to be inverted.
Transmission of the opposite value of A-bit than expected or set. In this
case the next transmitted A-bit is cleared to 0 if an RAI should be
transmitted, and set to 1 if RAI is not expected (done by inverting the next
A-bit before transmission).
Set to
Table
1
2-5.
Transmission of opposite of the expected code in FEBE
bits (the three C-bits in Subframe 4). When FEBE bits
are set to be internally-automatically generated,
setting a FEBE error insertion results in transmission
of a 111 code (no error code) in FEBE bits of a single
M-frame (at the next opportunity) if a frame error or a
C-bit parity error is detected. Otherwise, it transmits
the value stored in FEBEC/PT[1:3] in the Feature1
Control register.
Description
Description
CX28342/3/4/6/8 Data Sheet
28348-DSH-001-B
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