cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 24

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

Figure 2-4.
2.3.2
The receiver recovers data by normalizing the input signal with an automatic gain control (AGC) circuit, removing
distortion with an equalizer, and extracting the data using a data slicer. The transfer function of the equalizer is
adjusted based on the average peak value of the input signal. The AGC maintains the equalizer’s average peak
output level to a constant value. The data slicer compares the equalizer output to a threshold value equal to 50% of
the average peak equalizer output level and produces both positive and negative pulse detect signals. The data
slicer outputs are re-timed using the recovered clock and routed to the RZCS decoder (or to the JAT).
2.3.2.1
Optionally, the data slicer outputs, before re-timing, can be routed directly to the RPOSO and RNEGO digital output
pins. This option (raw receive mode) is selected by asserting the RAWMD [n] pin in Hardware Mode or by asserting
the RAWMD register bit [RLIU_CR; addr n1] in Host Mode. In raw receive mode, RCKO is replaced by the logical
OR of the RPOSO and RNEGO output signals, with CLK_POL set to zero. Otherwise, with CLK_POL set to 1,
RCKO is the logical NOR of the RPOSO and RNEGO.
This mode is useful in applications which provide external clock and data recovery.
mode receiver signals.
29380-DSH-001-B
Receiver Signals
Data Recovery
Raw Receive Mode
CLK_POL = 0
(Unipolar)
(Unipolar)
Equalized
Received
(Bipolar)
(Bipolar)
Internal
RPOSO
RNEGO
RDATO
Signal
RCKO
BPV
Preliminary Information / Mindspeed Proprietary and Confidential
1
Mindspeed Technologies
Data Slicer Level
(50% of Peak)
1
1
0
1
®
1
0
BPV
1
Figure 2-5
1
Circuit Description
illustrates the raw
16