cx28380 Mindspeed Technologies, cx28380 Datasheet - Page 54

• Manufacturer Part Number: cx28380
• Description: Cn8380 Quad T1/e1 Line Interface
• Manufacturer: Mindspeed Technologies

3.3
10, 20, 30, 40—Jitter Attenuator Configuration (JAT_CR)
T1/E1
JEN
JDIR
JCENTER
JSIZE[2:0]
29380-DSH-001-B
T1/
7
E1
T1/E1 Select
T1/E1 selects the nominal line rate (shown below), while the exact receive and transmit line rate
frequencies are independently determined by their respective input clock or data references.
The actual receive and transmit line frequency can vary within defined tolerances.
Jitter Attenuator Enable
by JDIR bit).
Select JAT Path—Applicable only when the JAT is enabled (see JEN description). JAT elastic
store is placed in either the receive or transmit path.
Force JAT to Center
the elastic store read pointer to one-half the programmed JSIZE. JCENTER is typically written
at power-up. JCENTER can optionally be asserted after recovery from a loss of signal (RLOS or
RALOS) or in response to a transmit loss of clock (TLOC), or after recovering from a persistent
JAT elastic store error (JERR). The JCENTER bit is self clearing.
JAT Elastic Store Size—Selects the maximum depth of the JAT elastic store. The 64-bit depth is
sufficient to meet jitter attenuation requirements in all cases. However, in cases where an
external reference is selected or a narrow loop bandwidth is programmed, the elastic store
depth can tolerate up to
Per Channel Registers
0 = 2.048 MHz line rate (E1)
1 = 1.544 MHz line rate (T1)
0 = Disable JAT
1 = Enable JAT
0 = JAT in TX path
1 = JAT in RX direction, jitter attenuated recovered clock output on RCKO
0 = normal operation
1 = recenter JAT elastic store
—
6
JSIZE
Preliminary Information / Mindspeed Proprietary and Confidential
000
001
010
011
1xx
—
Enables receive and transmit circuits to operate at either the T1 or E1 line rate.
JEN
5
—
Mindspeed Technologies
Elastic Store Size
Writing a 1 to JCENTER resets the elastic store write pointer and forces
—
±
JEN enables the JAT in the receive or the transmit path (determined
64 UI (128 bits) of accumulated phase offset.
128 Bits
16 Bits
32 Bits
64 Bits
8 Bits
JDIR
4
JCENTER
3
®
JSIZE[2]
2
JSIZE[1]
1
Registers
JSIZE[0]
0
R/W
46