lxt975 Intel Corporation, lxt975 Datasheet - Page 27

• Manufacturer Part Number: lxt975
• Description: Fast Ethernet 10/100 Quad Transceivers
• Manufacturer: Intel Corporation

2.3
2.3.1
2.3.2
Datasheet
Per Port (Fiber) Configuration
Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. Per-port settings override the global
pin settings.
100FX Full-Duplex
Operation.
100FX Half-Duplex
Operation.
Global (Twisted-Pair) Configuration
Force 100TX Full-Duplex
Operation on all ports.
Force 100TX Half-Duplex
Operation on all ports.
Force 10T Full-Duplex
Operation on all ports.
Force 10T Half-Duplex
Operation on all ports.
1. Refer to
2. Refer to
3. When SD/TPn is set High or to PECL levels, auto-negotiation is disabled and FDE_FX determines the duplex mode of the
4. CFG_2, CFG_0, and SD/TPn must all be set for 100TX operation.
5. Fiber configuration must be selected on a per-port basis.
port.
Table 17. Configuring the LXT974/975 with Auto-Negotiation Disabled
Desired Configuration
Table 15
Table 16
Initialization
At power-up or reset, the LXT974/975 performs the initialization as shown in
mode selection is provided via the MDDIS pin as shown in
High, the LXT974/975 operates in Manual Control Mode. When MDDIS is Low, the LXT974/975
operates in MDIO Control Mode.
MDIO Control Mode
In the MDIO Control Mode, the LXT974/975 uses the Hardware Control Interface to set up initial
(default) values of the MDIO registers. The MDIO Register set for the LXT974/975 is described in
Table 44
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15). Once initial values
are set, bit control reverts to the MDIO interface.
Manual Control Mode
In the Manual Control Mode, LXT974/975 disables direct write operations to the MDIO registers
via the MDIO interface. The Hardware Control Interface is continuously monitored and the MDIO
registers are updated accordingly.
for basic configurations.
for Hardware Control Interface functions advertised when auto-negotiation is enabled.
4
4
through
1,2
Table
5
per port
SD/TPn
High or
High or
PECL
PECL
Low
Low
Low
Low
55. Specific bits in the registers are referenced using an “X.Y” notation,
3
3
Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Ignored
Ignored
CFG_2
global
Low
Low
Low
Low
Pin Settings
Ignored
Ignored
CFG_0
global
High
High
Low
Low
Ignored
Ignored
global
FDE
High
High
Low
Low
Table
FDE_FX
Ignored
Ignored
Ignored
Ignored
18. When MDDIS (pin 100) is
High
Low
0.8
1
0
1
0
1
0
Figure
MDIO Registers
0.13
11. Control
1
1
1
1
0
0
19.2
1
1
0
0
0
0
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