AD6231 AD [Analog Devices], AD6231 Datasheet - Page 9

• Manufacturer Part Number: AD6231
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
−V
−V
−V
−V
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8253 can be set using WR as a latch,
allowing other devices to share A0 and A1. Figure 7 shows a
schematic using this method, known as latched gain mode. The
AD8253 is in this mode when WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0 and
A1 are read on the downward edge of the WR signal as it
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table listing in Table 6 for more on these gain changes.
S
S
S
S
Figure 7. Latched Gain Mode, G = 1000
A1
Low
Low
High
High
A0
Low
High
Low
High
A0, A1
WR
Gain
1
10
100
1000
Figure 8. Timing Diagram for Latched Gain Mode
t
WR-HIGH
Rev. prA | Page 9 of 10
t
SU
t
HD
t
WR-LOW
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
High to Low
High to Low
High to Low
High to Low
Low to Low
Low to High
High to High
1
Upon power-up, the AD8253 defaults to a gain of 1 when in
latched gain mode. In contrast, if the AD8253 is configured in
transparent gain mode, it starts at the gain indicated by the
voltage levels on A0 and A1 upon power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, t
WR latches in the gain. Similarly, they must be held for a
minimum hold time of t
ensure that the gain is latched in correctly. After t
may change logic levels but the gain does not change (until the
next downward edge of WR ). The minimum duration that WR
can be held high is t
duration that WR can be held low. Digital timing specifications
are listed in Table 2. The time required for a gain change is
dominated by the settling time of the amplifier. A timing
diagram is shown in Figure 8.
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8253. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog
portions of the board.
X = don’t care.
A1
Low
Low
X
X
X
High
High
WR
1
1
1
-HIGH
HD
after the downward edge of WR to
, and t
SU
A0
Low
High
Low
High
X
X
X
, before the downward edge of
1
1
1
WR
-LOW
Gain
Change to 1
Change to 10
Change to 100
Change to 1000
No Change
No Change
No Change
is the minimum
HD
, A0 and A1
AD8253