ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 40

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Interrupts
7.5
7.5.1
40/188
Figure 21. Nested interrupt management
Interrupt registers
CPU CC register interrupt bits
Table 14.
Table 15.
1. TRAP and RESET events can interrupt a level 3 program.
These two bits indicate the current interrupt software priority (see
set/cleared by hardware when entering in interrupt. The loaded value is given by the
corresponding bits in the interrupt software priority registers (ISPRx).
They can be also set/cleared by software with the RIM, SIM, HALT, WFI, IRET and
PUSH/POP instructions (see
CPU CC
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Bit Name
5
3
R/W
7
1
I1
I0
Interrupt software priority
Software Interrupt Priority 1
Software Interrupt Priority 0
CPU CC register interrupt bits description
Interrupt software priority levels
11 / 10
R/W
Main
RIM
6
1
IT2
(1)
IT1
R/W
I1
5
Table 17: Dedicated interrupt instruction
IT4
TRAP
R/W
H
4
IT4
IT0
Function
IT3
R/W
I0
3
IT1
Level
High
Low
IT2
10
R/W
N
2
Main
Software
priority
level
Reset value: 111x 1010(xAh)
Table
I1
1
0
0
1
set).
3
3
2
1
3
3
3/0
15) and are
R/W
1
Z
I1
1 1
1 1
0 0
0 1
1 1
1 1
ST72324B
I0
I0
R/W
0
1
0
1
C
0