ST72F324BJ STMICROELECTRONICS [STMicroelectronics], ST72F324BJ Datasheet - Page 44

• Manufacturer Part Number: ST72F324BJ
• Description: 8-bit MCU, 3.8 to 5.5 V operating range with 8 to 32 Kbyte Flash/ROM, 10-bit ADC, 4 timers, SPI, SCI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Interrupts
7.6.2
44/188
External interrupt control register (EICR)
Table 18.
Table 19.
EICR
7:6 IS1[1:0]
4:3 IS2[1:0]
1:0
Bit
5
2
IS11
IS11
R/W
0
0
1
1
7
Name
IPB
IPA
-
EICR register description
Interrupt sensitivity - ei2
IS10
ei2 and ei3 sensitivity
Interrupt Polarity (for port B)
ei0 and ei1 sensitivity
Interrupt Polarity (for port A)
Reserved, must always be kept cleared
0
1
0
1
IS10
R/W
The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following
external interrupts:
- ei2 for port B [3:0] (see
- ei3 for port B4 (see
Bits 7 and 6 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of port B [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion
1: Sensitivity inversion
The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following
external interrupts:
- ei0 for port A[3:0] (see
- ei1 for port F[2:0] (see
Bits 4 and 3 can only be written when I1 and I0 of the CC register are both set to 1
(level 3).
This bit is used to invert the sensitivity of port A [3:0] external interrupts. It can be
set and cleared by software only when I1 and I0 of the CC register are both set to 1
(level 3).
0: No sensitivity inversion.
1: Sensitivity inversion.
6
Falling edge and low level
R/W
IPB
5
Falling edge only
Rising edge only
IPB bit = 0
Table
IS21
R/W
Table
Table
Table
4
20)
External interrupt sensitivity
22)
21)
19)
Rising and falling edge
Function
IS20
R/W
3
R/W
IPA
Rising edge and high level
2
Reset value: 0000 0000 (00h)
Falling edge only
Rising edge only
IPB bit = 1
1
Reserved
-
ST72324B
0