ssd1329 ETC-unknow, ssd1329 Datasheet - Page 14

• Manufacturer Part Number: ssd1329
• Description: 128 X 128 Oled Segment / Common Driver With Controller Equips With 16 Gray Scale Levels And 64 Hard Icon Lines
• Manufacturer: ETC-unknow

7
Key:
Pin Name Pin Type
RES#
CS#
D/C#
E (RD#)
R/W#
(WR#)
D[7:0]
BS[2:0]
V
V
V
CL
CLS
V
Solomon Systech
DDIO
DD
SS,
CC
V
PIN DESCRIPTIONS
LSS
I = Input
O =Output
IO = Bi-directional (input/output)
P = Power pin
I
I
I
I
I
IO
I
P
P
P
IO
I
P
Description
This pin is reset signal input. When the pin is LOW, initialization of the chip is executed.
Keep this pin HIGH during normal operation.
This pin is the chip select input. The chip is enabled for MCU communication only when
CS# is pulled LOW.
This pin is Data/Command control pin. When the pin is pulled HIGH, the data at D[7:0] is
treated as data. When the pin is pulled LOW, the data at D[7:0] will be transferred to the
command register. For detail relationship to MCU interface signals, please refer to the
Timing Characteristics Diagrams in Figure 13-1, Figure 13-2, Figure 13-3.
This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin
will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled
HIGH and the chip is selected.
When connecting to an 8080-microprocessor, this pin receives the Read (RD#) signal. Data
read operation is initiated when this pin is pulled LOW and the chip is selected.
This pin is MCU interface input. When interfacing to a 6800-series microprocessor, this pin
will be used as Read/Write (R/W#) selection input. Read mode will be carried out when this
pin is pulled HIGH and write mode will be carried out when LOW.
When 8080 interface mode is selected, this pin will be the Write (WR#) input. Data write
operation is initiated when this pin is pulled LOW and the chip is selected.
These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus.
MCU bus interface selection pins. Please refer to Table 7-2 for the details of the selection.
This pin is a power supply pin of I/O buffer. It should be connected to V
All I/O signal should have voltage high reference to V
BS2, CLS, CL, D[7:0], interface signals…) pull HIGH, they should be connected to V
Power Supply pin. It must be connected to external source.
These pins are ground pin and also act as ground reference for the logic pins. They must be
connected to external ground.
This pin is the system clock input. When internal oscillator is disabled, this pin receives
display clock signal from external clock source. When internal clock is enabled, this pin
should be left open and nothing should be connected to this pin.
This pin is internal clock enable. When this pin is pulled HIGH, internal oscillator is selected.
The internal clock will be disabled when it is pulled LOW, an external clock source must be
connected to CL pin for normal operation.
This is the most positive voltage supply pin of the chip. It is supplied either by external high
voltage source or internal booster.
Table 7-1 : Pin Descriptions
Dec 2005 P 14/58
DDIO
. When I/O signal pins (BS0, BS1,
Rev 1.1
DD
or external source.
SSD1329
DDIO
.