ssd1329 ETC-unknow, ssd1329 Datasheet - Page 22

• Manufacturer Part Number: ssd1329
• Description: 128 X 128 Oled Segment / Common Driver With Controller Equips With 16 Gray Scale Levels And 64 Hard Icon Lines
• Manufacturer: ETC-unknow

8.3
This module is an On-Chip low power RC oscillator circuitry. The operation clock (CLK) can be generated
either from internal oscillator or external source CL pin. This selection is done by CLS pin. If CLS pin is
pulled HIGH, internal oscillator is chosen and CL should be left open. Pulling CLS pin LOW disables
internal oscillator and external clock must be connected to CL pins for proper operation. When the internal
oscillator is selected, its output frequency F
The display clock (DCLK) for the Display Timing Generator is derived from CLK. The division factor “D”
can be programmed from 1 to 16 by command B3h
The frame frequency of display is determined by the following formula.
where
•
•
•
•
If the frame frequency is set too low, flickering may occur. On the other hand, higher frame frequency
leads to higher power consumption on the whole system.
Solomon Systech
D stands for clock divide ratio. It is set by command B3h A[3:0]. The divide ratio has the range from 1 to
16.
K is row period. It is configured by command B2h. This value should comply with following condition.
Number of multiplex ratio is set by command A8h. The power ON reset value is 7Fh.
F
setting results in faster frequency.
OSC
Oscillator Circuit and Display Time Generator
is the oscillator frequency. It can be changed by command B3h A[7:4]. The higher the register
CL
Figure 8-7 : Oscillator Circuit and Display Time Generator
Oscillator
Internal
Fosc
K ≥ Phase 1 + Phase 2 + Phase 3 + GS15
F
FRM
OSC
=
DCLK = F
can be changed by command B3h, please refer to Table 9-1.
D
×
CLS
K
M
U
X
×
OSC
No.
F
CLK
osc
/ D
of
Mux
Dec 2005 P 22/58
Divider
Rev 1.1
Clock
Display
DCLK
SSD1329