ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 126

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the CPU bus clock (not a
divided version of CLKI) e.g. SH-3, SH-4.
11.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The SSD1908 is designed with
efficient power saving control for clocks (clocks are turned off when not used).
Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and
so reduces screen update performance. For a balance of power saving and performance, the MCLK should be
configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable CPU
cycle latency.
The source clock options for MCLK may be selected as in the following table.
11.1.3 PCLK
PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame
rate of the LCD panel. See Section 13 ”Frame Rate Calculation” for details on the relationship between PCLK and
frame rate.
Some flexibility is possible in the selection of PCLK. Firstly, LCD panels typically have a range of permissible frame
rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non-
display periods to lower the frame-rate to its optimal value.
The source clock options for PCLK may be selected as in the Table 11-3 : PCLK Clock Selection.
Solomon Systech
Source Clock Options
BCLK ÷ 2
BCLK ÷ 3
BCLK ÷ 4
BCLK
Table 11-2 : MCLK Clock Selection
MCLK Selection (REG[04h])
Oct 2003
00h
10h
20h
30h
P 116/116 Rev 1.0
SSD1908