ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 21

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

SSD1908
RD/WR#
RESET#
WAIT#
Name
RD#
BS#
Pin
Type
O
I
I
I
I
Rev 1.0
TQFP
Pin #
12
17
13
8
9
P 11/11
TFBGA
Pin #
G6
G7
H5
H6
J5
Oct 2003
Cell
LT2
LIS
LIS
LIS
LIS
RESET#
State
Hi-Z
1
1
1
0
This input pin has multiple functions.
•
•
•
•
•
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
•
•
•
•
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
•
•
•
•
•
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
During a data transfer, this output pin is driven active to force
the system to insert wait states. It is driven inactive to indicate
the completion of a data transfer. WAIT# is released to the
high impedance state after the data transfer is complete. Its
active polarity is configurable. A pull-up or pull-down resistor
should be used to resolve any data contention issues. See
Table 5-6 : Summary of Power-On/Reset Options.
•
•
•
•
•
•
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Active low input to set all internal registers to the default state
and to force all signals to their inactive states. It is
recommended to place a
Note : When reset state is released (RESET# = “H”),
normal operation can be started after 3 BCLK period.
For Generic #1, this pin must be tied to IOV
For Generic #2, this pin must be tied to IOV
For MC68K #1, this is an input of the address strobe
(AS#).
For DragonBall, this pin must be tied to IOV
For SH-3/SH-4, this is input of the bus start signal (BS#).
For Generic #1, this is an input of the read command for
the upper data byte (RD1#).
For Generic #2, this pin must be tied to IOV
For MC68K #1, this is an input of the R/W# signal.
For DragonBall, this pin must be tied to IOV
For SH-3/SH-4, this is input of the RD/WR# signal. The
SSD1905 needs this signal for early decode of the bus
cycle.
For Generic #1, this is an input of the read command for
the lower data byte (RD0#).
For Generic #2, this is an input of the read command
(RD#).
For MC68K #1, this pin must be tied to IOV
For DragonBall, this is an input of the output enable
(OE#).
For SH-3/SH-4, this is input of the read signal (RD#).
For Generic #1, this pin outputs the wait signal (WAIT#).
For Generic #2, this pin outputs the wait signal (WAIT#).
For MC68K #1, this pin outputs the data transfer
acknowledge signal (DTACK#).
For DragonBall, this pin outputs the data transfer
acknowledge signal (DTACK#).
For SH-3 mode, this pin outputs the wait request signal
(WAIT#).
For SH-4 mode, this pin outputs the device ready signal
(RDY#).
Description
0.1µF capacitor to V
Solomon Systech
DD
SS
DD
DD
DD
DD
DD
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