ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 38

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

REG[1Fh] bits 1-0,
REG[1Eh] bits 7-0
Bit 7
Bits 6-0
Reset
Reset
Reset
Type
state
Type
state
Type
state
Solomon Systech
Bit
Bit
Bit
Vertical Display Period Start Position Register 0
Vertical Display Period Start Position Register 1
LLINE Pulse Width Register
Period Start
Position Bit
Vertical
Display
Polarity
LLINE
Pulse
RW
RW
NA
7
7
0
7
0
0
7
0
Pulse Width
Period Start
Position Bit
Vertical
Display
LLINE
Vertical Display Period Start Position Bits [9:0]
These bits specify the Vertical Display Period Start Position in 1 line resolution.
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display
Interface”.
LLINE Pulse Polarity
This bit determines the polarity of the horizontal sync signal. The horizontal sync signal
is typically named as LLINE or LP or HSD, depending on the panel type.
When this bit = 0, the horizontal sync signal is active low.
When this bit = 1, the horizontal sync signal is active high.
LLINE Pulse Width Bits [6:0]
These bits specify the width of the panel horizontal sync signal, in number of PCLK.
The horizontal sync signal is typically named as LLINE or LP or HSD, depending on
the panel type.
LLINE Pulse Width in PCLK = Bits [6:0] + 1
Note
For panel AC timing and timing parameter definitions, see Section 10.4 “Display Interface”.
Bit 6
RW
RW
NA
6
6
0
6
0
0
6
0
Pulse Width
Period Start
Position Bit
Vertical
Display
LLINE
Bit 5
RW
RW
NA
5
5
0
5
0
0
5
0
Pulse Width
Period Start
Position Bit
Vertical
Display
LLINE
Bit 4
RW
RW
NA
4
4
0
4
0
0
4
0
Oct 2003
Pulse Width
Period Start
Position Bit
Vertical
Display
LLINE
Bit 3
RW
RW
NA
3
3
0
3
0
0
3
0
P 28/28
Pulse Width
Period Start
Position Bit
Vertical
Display
LLINE
Bit 2
RW
RW
NA
2
2
0
2
0
0
2
0
Rev 1.0
Pulse Width
Period Start
Period Bit 9
Position Bit
Position
Vertical
Vertical
Display
Display
LLINE
Start
Bit 1
RW
RW
RW
1
1
0
1
0
1
0
SSD1908
REG[1Eh]
REG[1Fh]
REG[20h]
Pulse Width
Period Start
Period Bit 8
Position Bit
Position
Vertical
Vertical
Display
Display
LLINE
Start
Bit 0
RW
RW
RW
0
0
0
0
0
0
0