ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 28

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

7
This section discusses how and where to access the SSD1908 registers. It also provides detailed information
about the layout and usage of each register.
7.1
The SSD1908 registers are memory-mapped. When the system decodes the input pins as CS# = 0 and M/R# = 0,
the registers may be accessed. The register space is decoded by A[17:0].
7.2
Unless specified otherwise, all register bits are set to 0 during power-on or software reset (REG[A2h] bit 0 = 1). All
bits marked “0” should be programmed as zero. All bits marked “1” should be programmed as one.
Key :
7.2.1 Read-Only Configuration Registers
Bits 7-0
Bits 7-0
Reset
Reset
Type
Type
Solomon Systech
state
state
Bit
Bit
Registers
Register Mapping
Register Descriptions
RO : Read Only
WO : Write Only
RW : Read / Write
NA : Not Applicable
X : Don’t care
Configuration Readback Register
Display Buffer Size Register
CF7 Status
Display
Buffer
Size
Bit 7
RO
RO
X
7
0
7
CF6 Status
Display
Display Buffer Size Bits [7:0]
This register indicates the size of the SRAM display buffer in 4K byte multiple. The
SSD1908 display buffer is 256K bytes and therefore this register returns a value of 40h
(64).
Value of this register
CF[7:0] Status
These status bits return the status of the configuration pins CF[7:0]. CF[5:0] are
latched at the rising edge of RESET# or software reset (REG[A2h] bit 0 = 1).
Buffer
Size
Bit 6
RO
RO
X
6
1
6
CF5 Status
Display
Buffer
Size
Bit 5
RO
RO
X
5
0
5
= display buffer size ÷ 4K bytes
= 256K bytes ÷ 4K bytes
= 40h (64)
CF4 Status
Display
Buffer
Size
Bit 4
RO
RO
X
4
0
4
Oct 2003
CF3 Status
Display
Buffer
Size
Bit 3
RO
RO
X
3
0
3
P 18/18
CF2 Status
Display
Buffer
Size
Bit 2
RO
RO
X
2
0
2
Rev 1.0
CF1 Status
Display
Buffer
Size
Bit 1
RO
RO
X
1
0
1
SSD1908
CF0 Status
REG[01h]
REG[02h]
Display
Buffer
Size
Bit 0
RO
RO
X
0
0
0