ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 62

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

7.2.10 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration
Registers
Note
For further information on PWMCLK, see Section 11.1.4 “PWMCLK”.
Bit 7 and Bit 4
x = don’t care
Reset
Type
state
Solomon Systech
Bit
PWM Clock / CV Pulse Control Register
PWM Clock
Force High
CV Pulse Enable
PWM Clock Enable
RW
0
7
Bit 7
PWMCLK
0
0
1
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the LPWMOUT pin and PWM Clock circuitry as Table 7-15 : PWM
Clock Control.
When LPWMOUT is forced low or forced high it can be used as a general purpose
output.
Note
The PWM Clock circuitry is disabled when Power Saving Mode is enabled.
NA
6
0
0
m = PWM Clock Divide Select value
x = CV Pulse Divide Select value
Figure 7-4 : PWM Clock/CV Pulse Block Diagram
Bit 4
Clock Source/ 2
Clock Source/ 2
PWM Clock
Divider
X
1
0
CV Pulse
Divider
NA
5
0
0
Table 7-15 : PWM Clock Control
m
x
Divided
Clock
Divided
Clock
PWM Clock
Enable
RW
PW M Clock Force High
4
0
n = PWM Clock Duty Cycle
CV Pulse Force High
(controlled by REG[B1h] and REG[B3h])
y = Burst Length value
PWM Duty Cycle
Modulation
CV Pulse Burst
Generation
Duty = n / 256
y-pulse burst
Oct 2003
PWM Clock circuitry enabled
Force High
CV Pulse
LPWMOUT forced high
LPWMOUT forced low
RW
3
0
P 52/52
Result
CV Pulse
Status
Burst
RO
2
0
Rev 1.0
Frequency =
Clock Source / (2
Frequency =
Clock Source / (2
Burst Start
CV Pulse
RW
1
0
LPWMOUT
m
x
LCVOUT
X 2)
X 256)
SSD1908
REG[B0h]
CV Pulse
Enable
RW
0
0