ssd1908 Solomon Systech Limited:, ssd1908 Datasheet - Page 44

• Manufacturer Part Number: ssd1908
• Description: Lcd Drivers,lcd Controllers
• Manufacturer: Solomon Systech Limited:

Bits 7-0
Bits 7-0
Reset
Type
state
Solomon Systech
Bit
GPIO2 Pulse Delay Register
Delay Bit 7
GPIO2
* For REG[22] = 0,
START = 0 Ts if REG[38h] bit 7 = 1 and REG[3C] = 05
STOP = 0 Ts if REG[38h] bit 7 = 1 and REG[3E] = 02
LDATA[7:0]
RW
7
0
LSHIFT
LLINE
LDEN
Delay Bit 6
GPIO2
GPIO0 / LDEN Pulse Stop [7:0]
When 320x240 HR-TFT panel is selection, these bits specify the stop offset of the
GPIO0 signal within a line, in 1 pixel resolution. See Figure 7-2 : GPIO offset for
320x240 HR-TFT.
When Analog TFT panel is selection, these bits specify the stop offset of the LDEN
signal within a line, in 1 pixel resolution. This register is incremented by 0.5 Ts. See
Figure 7-1 : LDEN offset for Analog TFT.
Note
When 320x240 HR-TFT panel is selection, this register must be programmed such that
the following condition is fulfilled.
GPIO0 Pulse Width = (STOP – START + 1) Ts
This register is effective for GPIO Preset enabled and 320x240 HR-TFT panel (REG[38h]
bit 5 = 1 and REG[10h] bits 3-0 = 1010) or LDEN Preset enabled and Analog TFT panel
(REG[10h] bits 2-0 = 100 and REG[38h] bit 7 = 1).
For panel AC timing and timing parameter definitions, see Section 10.4.9 “Generic HR-
TFT Panel Timing ” and Section 10.4.10 ”160x234 Analog TFT Panel Timing (e.g.
UP025D10)”.
GPIO2 Pulse Delay [7:0]
These bits specify the pulse delay of the GPIO2 signal within a line, in 1 pixel
resolution. See Figure 7-2 : GPIO offset for 320x240 HR-TFT.
Note
This register is effective for 320x240 HR-TFT panels and GPIO Preset enabled only
(REG[10h] bits 3-0 = 1010 and REG[38h] bit 5 = 1).
RW
6
0
GPIO0 Pulse Stop Value, REG[3Eh] ≥ GPIO0 Pulse Start Value, REG[3Ch]
START
Delay Bit 5
Figure 7-1 : LDEN offset for Analog TFT
GPIO2
RW
5
0
Delay Bit 4
GPIO2
RW
4
0
1-R1
Oct 2003
1-G1
Delay Bit 3
GPIO2
RW
3
0
P 34/34
Delay Bit 2
1-B160
GPIO2
RW
2
0
Rev 1.0
STOP
Delay Bit 1
GPIO2
RW
1
0
SSD1908
REG[40h]
Delay Bit 0
GPIO2
RW
0
0