gl850g Genesys Logic, gl850g Datasheet - Page 12

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gl850g

Manufacturer Part Number
gl850g
Description
Gl850g Usb 2.0 Low-power Hub Controller
Manufacturer
Genesys Logic
Datasheet

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3.3 Pin Descriptions
©2000-2008 Genesys Logic Inc. - All rights reserved.
OVCUR1~4#
PWREN1~4#
Pin Name
Pin Name
DM0,DP0
DM1,DP1
DM2,DP2
DM3,DP3
DM4,DP4
RREF
Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to
Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type Pin# Pin Name Type
1
2
3
4
5
6
7
GL850G Design Guideline.
AVDD
DM2
DP2
RREF
AVDD
X1
X2
48Pin#
48Pin#
42,40,
43,41,
17,18
21,22
30,28
31,29
9,10
3,4
5,6
11
GL850G
GL850G
B
B
B
O
P
P
I
10 AVDD
11 DM4
12 DP4
13 RESET#
14 TEST
8 DM3
9 DP3
Table 3.2
28Pin#
28Pin#
Table 3.3 - Pin Descriptions
25,26
27,28
11,12
19,21
20,22
2,3
8,9
4
- - - -
HUB Interface
USB Interface
GL850G USB 2.0 Low-Power HUB Controller
G L850G 28 Pin List
I/O Type
I/O Type
I_5V 20 PWREN2#
I_5V
(pu)
B
B
B
B
P
I
B
B
B
B
B
B
O
15 GND
16 DVDD
17 PSELF
18 PGANG
19 OVCUR2#
21 OVCUR1#
USB signals for USPORT
USB signals for DSPORT1
USB signals for DSPORT2
USB signals for DSPORT3
USB signals for DSPORT4
A 680 resister must be connected between
RREF and analog ground (AGND).
Active low. Over current indicator for
DSPORT1~4
OVCUR1# is the only over current flag for
GANG mode.
Active low. Power enable output for
DSPORT1~4
PWREN1# is the only power-enable output for
GANG mode.
I_5V 24 V33
I_5V 26
I_5V 28
Description
Description
B
O
P
P
22 PWREN1#
23 V5
25
27
DM0
DP0
DM1
DP1
Page 12
O
B
B
B
B
P
P

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