BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 35

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

BS85B12-3/BS85C20-3
Touch Key Flash MCU with LCD/LED Driver
Note:
Rev. 1.00
Bit 7, 6
Bit 5~0
Bit 7
Bit 6~0
Bit 7~4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Name
Name
POR
POR
POR
R/W
R/W
R/W
Bit
Bit
Bit
The WREN, WR, RDEN and RD can not be set to 1 at the same time in one instruction. The WR and RD can
not be set to 1 at the same time.
EEA Register
EEC Register
BS85B12-3
BS85C20-3
unimplemented, read as 0
Data EEPROM address
Data EEPROM address bit 5~bit 0
unimplemented, read as 0
Data EEPROM address
Data EEPROM address bit 6~bit 0
unimplemented, read as 0
WREN: data EEPROM write enable
This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations.
WR: EEPROM write control
This is the Data EEPROM Write Control Bit and when set high by the application program will
activate a write cycle. This bit will be automatically reset to zero by the hardware after the write
cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high.
RDEN: Data EEPROM read enable
This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read
operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations.
RD: EEPROM read control
This is the Data EEPROM Read Control Bit and when set high by the application program will
activate a read cycle. This bit will be automatically reset to zero by the hardware after the read
cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high.
7
7
7
0: disable
1: enable
0: Write cycle has finished
1: Activate a write cycle
0: disable
1: enable
0: read cycle has finished
1: activate a read cycle
R/W
D6
6
6
x
6
R/W
R/W
D5
D5
5
x
5
x
5
R/W
R/W
D4
D4
29
4
4
4
x
x
WREN
R/W
R/W
R/W
D3
D3
3
3
3
0
x
x
R/W
R/W
R/W
WR
D2
D2
2
x
2
x
2
0
RDEN
R/W
R/W
R/W
D1
D1
1
x
1
x
1
0
February 1, 2011
x unknown
x unknown
R/W
R/W
R/W
RD
D0
D0
0
0
0
0
x
x