BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 73

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

BS85B12-3/BS85C20-3
Touch Key Flash MCU with LCD/LED Driver
Rev. 1.00
Bit 3
Bit 2
Bit 1
Bit 0
Compact Type TM Operating Modes
Compare Match Output Mode
The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode,
PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits
in the TMnC1 register.
To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In
this mode once the counter is enabled and running it can be cleared by three methods. These are a
counter overflow, a compare match from Comparator A and a compare match from Comparator P.
When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a
compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows
the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and
Comparator P respectively, will both be generated.
In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state
when a certain compare match condition occurs. The PWM output function is modified by
changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only
after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and
TnIO0 bits are changed when the TM is running
TnOC: TPn_0, TPn_1 Output control bit
Compare Match Output Mode
PWM Mode
This is the output control bit for the TM output pin. Its operation depends upon whether TM is
being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is
in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of
the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM
signal is active high or active low.
TnPOL: TPn_0, TPn_1 Output polarity Control
This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the
Timer/Counter Mode.
TnDPX: TMn PWM period/duty Control
This bit, determines which of the CCRA and CCRP registers are used for period and duty
control of the PWM waveform.
TnCCLR: Select TMn Counter clear condition
This bit is used to select the method which clears the counter. Remember that the Compact TM
contains two comparators, Comparator A and Comparator P, either of which can be selected to
clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a
compare match occurs from the Comparator A. When the bit is low, the counter will be cleared
when a compare match occurs from the Comparator P or with a counter overflow. A counter
overflow clearing method can only be implemented if the CCRP bits are all cleared to zero.
The TnCCLR bit is not used in the PWM Mode.
0: Initial low
1: Initial high
0: Active low
1: Active high
0: Non-invert
1: Invert
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
0: TMn Comparatror P match
1: TMn Comparatror A match
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February 1, 2011