BS85B12-3 HOLTEK [Holtek Semiconductor Inc], BS85B12-3 Datasheet - Page 37

• Manufacturer Part Number: BS85B12-3
• Description: Touch Key Flash Type 8-Bit MCU with LCD/LED Driver
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

BS85B12-3/BS85C20-3
Touch Key Flash MCU with LCD/LED Driver
Rev. 1.00
Programming Considerations
Programming Examples
Reading Data from the EEPROM - Polling Method
Writing Data to the EEPROM - Polling Method
Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced
by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank
Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM
control register exist. Although certainly not necessary, consideration might be given in the application
program to the checking of the validity of new write data by a simple read back process.
When writing data the WR bit must be set high immediately after the WREN bit has been set high, to
ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a
write cycle is executed and then re-enabled after the write cycle starts.
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
SET IAR1.1
SET IAR1.0
BACK:
SZ
JMP BACK
CLR IAR1
CLR BP
MOV A, EEDATA
MOV READ_DATA, A
CLR EMI
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ
JMP BACK
CLR IAR1
CLR BP
IAR1.0
IAR1.2
; user defined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM read/write
; move read data to register
; user defined address
; user defined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; Start Write Cycle - set WR bit - executed immediately
; after set WREN bit
; check for write cycle end
; disable EEPROM read/write
31
February 1, 2011