C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 189
![no-image](/images/no-image-200.jpg)
C505_9708
Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C505_9708.pdf
(227 pages)
- Current page: 189 of 227
- Download datasheet (2Mb)
8
The C505 offers enhanced fail save mechanisms, which allow an automatic recovery from software
upset or hardware failure :
8.1
To protect the system against software upset, the user’s program has to clear this watchdog within
a previously programmed time period. lf the software fails to do this periodical refresh of the
watchdog timer, an internal hardware reset will be initiated. The software can be designed so that
the watchdog times out if the program does not work properly. lt also times out if a software error is
based on hardware-related problems.
The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of
upto
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written. Figure 8-1 shows the block diagram of the watchdog timer unit.
Figure 8-1
Block Diagram of the Programmable Watchdog Timer
Semiconductor Group
– a programmable watchdog timer (WDT), with variable time-out period from 192 s up to
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
f
approx. 412.5 ms at 16 MHz.
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
OSC
f
OWDS
Fail Save Mechanisms
Programmable Watchdog Timer
OSC
External HW Reset
/192. The machine clock of the C505 is divided by two prescalers, a divide-by-two and a
/ 6
SWDT
WDTS
WDT
2
Control Logic
WDT Reset - Request
16
IP0 (A9 )
8-1
H
IEN0 (A8 )
IEN1 (B8 )
WDTPSEL
H
H
7
0
Fail Save Mechanisms
6
14
WDTREL (86 )
WDTL
WDTH
C505 / C505C
H
MCB03306
1997-08-01
7
8
0
f
OSC
/12
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