C505_9708 SIEMENS [Siemens Semiconductor Group], C505_9708 Datasheet - Page 197
C505_9708
Manufacturer Part Number
C505_9708
Description
8-Bit CMOS Microcontroller
Manufacturer
SIEMENS [Siemens Semiconductor Group]
Datasheet
1.C505_9708.pdf
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9
The C505 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.
9.1
The functions of the power saving modes are controlled by bits which are located in the special
function registers PCON and PCON1. The SFR PCON is located at SFR address 87 H . PCON1 is
located in the mapped SFR area (RMAP=1) at SFR address 88 H . Bit RMAP, which controls the
access to the mapped SFR area, is located in SFR SYSCON (B1 H ).
The bits PDE, PDS and IDLE, IDLS located in SFR PCON select the power down mode or the idle
mode, respectively. If the power down mode and the idle mode are set at the same time, power
down takes precedence. Furthermore, register PCON contains two general purpose flags. For
example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during
normal operation or during an idle. For this, an instruction that activates idle can also set one or both
flag bits. When idle is terminated by an interrupt, the interrupt service routine can examine the flag
bits.
Special Function Register PCON (Address 87 H)
Symbol
PDS
IDLS
SD
GF1
GF0
PDE
IDLE
Semiconductor Group
Bit No.
87 H
Power Saving Modes
Power Saving Mode Control Registers
MSB
SMOD
7
The function of the shaded bit is not described in this section.
Function
Power down start bit
The instruction that sets the PDS flag bit is the last instruction before entering
the power down mode
Idle start bit
The instruction that sets the IDLS flag bit is the last instruction before entering
the idle mode.
Slow down mode bit
When set, the slow down mode is enabled
General purpose flag
General purpose flag
Power down enable bit
When set, starting of the power down is enabled
Idle mode enable bit
When set, starting of the idle mode is enabled
PDS
6
IDLS
5
SD
4
9-1
GF1
3
GF0
2
PDE
Power Saving Modes
1
IDLE
Reset Value : 00 H
C505 / C505C
0
LSB
1997-08-01
PCON
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