LTC2421 LINER [Linear Technology], LTC2421 Datasheet - Page 18

• Manufacturer Part Number: LTC2421
• Description: 1-/2-Channel 20-Bit UPower No Latency ADCs in MSOP-10
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2421/LTC2422
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
(if EOC = 0) or t
during the falling edge of EOC). The value of t
if the device is using its internal oscillator (F
or HIGH). If F
quency f
HIGH before time t
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the con-
version result into external circuitry. EOC can be latched
on the first rising edge of SCK and the last bit of the con-
version result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH, and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
18
(INTERNAL)
SDO
SCK
CS
EOSC
CONVERSION
Hi-Z
, then t
O
EOCtest
is driven by an external oscillator of fre-
EOCtest
U
EOCtest
after EOC goes LOW (if CS is LOW
TEST EOC
EOCtest
, the device remains in the sleep
U
SLEEP
Hi-Z
is 3.6/f
<t
after the falling edge of CS
EOCtest
BIT 23
EOC
EOCtest
W
Figure 9. Internal Serial Clock, Single Cycle Operation
EOSC
CH0/CH1
BIT 22
ANALOG INPUT RANGE
(V
. If CS is pulled
, the first rising
ZS
REF
REFERENCE VOLTAGE
0V TO FS
ZS
SET
EOCtest
0
FS
= FS
SET
SET
= logic LOW
– 0.12V
SET
+ 0.1V TO V
U
+ 0.12V
SET
BIT 21
– ZS
SIG
– 100mV
REF
is 23 s
SET
1 F
2.7V TO 5.5V
REF
TO
)
CC
BIT 20
EXR
1
2
3
4
5
V
FS
CH1
ZS
CH0
CC
SET
SET
LTC2422
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 10. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2421/LTC2422’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external driver
on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2421/LTC2422’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
BIT 19
MSB
SDO
GND
SCK
DATA OUTPUT
CS
F
O
10
9
8
7
6
BIT 18
V
CC
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
BIT 4
V
CC
BIT 0
LSB
10k
20
CONVERSION
Hi-Z
TEST EOC
24212 F09
24212f
Hi-Z