S29CD016G SPANSION, S29CD016G Datasheet - Page 15

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

November 5, 2004 S29CD016_00_A4
Requirements for Reading Array Data
Simultaneous Read/Write
Operations Overview and Restrictions
The output voltage generated on the device is determined based on the V
(V
A V
level.
A V
To read array data from the outputs, the system must drive the CE# and OE#
pins to V
control and gates array data to the output pins. WE# should remain at V
The internal state machine is set for reading array data upon device power-up,
or after a hardware reset. This ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data on the device data
outputs. The device remains enabled for read access until the command register
contents are altered.
Address access time (t
data. The chip enable access time (t
stable CE# to valid data at the output pins. The output enable access time (t
is the delay from the falling edge of OE# to valid data at the output pins (assum-
ing the addresses are stable for at least t
least t
See
Refer to the AC Read Operations table for timing specifications and to
page 20
the active current specification for reading array data.
Overview
The Simultaneous Read/Write feature allows a program or erase operation to be
executed in one (busy) bank, while performing other operations in the other bank
(non-busy).
The Simultaneous Read/Write operation of this device was optimized for applica-
tions that could most benefit from this capability. These applications store code
in the larger bank, while storing data in the smaller bank. The best example of
this is when a Sector Erase Operation (as an embedded operation) in the smaller
(busy) bank occurs, while performing a Burst/synchronous Read Operation in the
larger (non-busy) bank.
Restrictions
The Simultaneous Read/Write function is tested by executing an embedded op-
eration in the small (busy) bank while performing other operations in the big
(non-busy) bank. However, the opposite case is neither tested nor valid. That is,
it is not tested by executing an embedded operation in the big (busy) bank while
performing other operations in the small (non-busy) bank. See the following ta-
bles,
on page 36
CCQ
CC
IO
““Reading Array Data in Non-burst Mode” on page
Table 2 on page
) level.
of 1.65–1.95 volts is targeted to provide for I/O tolerance at the 1.8 volt
and V
CE
–t
IL
for the timing diagram. I
OE
. CE# is the power control and selects the device. OE# is the output
A d v a n c e
IO
time).
of 2.5–2.75 volts makes the device appear as 2.5 volt-only.
16,
ACC
Table 18 on page
) is the delay from stable addresses to valid output
I n f o r m a t i o n
CC1
S29CD016G
CE
in the DC Characteristics table represents
) is the delay from stable addresses and
ACC
50,
–t
OE
Table 12 on page
time and CE# is asserted for at
42” for more information.
34, and
Table 1 on
Table 13
IH
.
OE
IO
)
15