AD723 Analog Devices, AD723 Datasheet - Page 12

• Manufacturer Part Number: AD723
• Description: 2.7 V to 5.5 V RGB-to-NTSC/PAL Encoder with Load Detect and Input Termination Switch
• Manufacturer: Analog Devices

AD723
Symbol
t
t
t
t
t
t
t
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NOTES
1
2
SW
SB
SM
MW
SR
RW
SD
DW
SS
BY
SC
BC
Input clock = 14.318180 MHz, STND pin = logic high.
Input clock = 17.734475 MHz, STND pin = logic low.
Name
Sync Width
Sync to Blanking
End
Sync to Modulator
Restore
Modulator Restore
Width
Sync to RGB DC
Restore
DC Restore Width
Sync to Delay Line
Reset
Delay Line Reset
Width
Sync Input to Luma
Sync Output
Blanking End to
LUMA Start
Sync to Colorburst
Blanking End to
CRMA Start
DELAY LINE RESET
(USER INPUTS)
HSYNC/VSYNC
(USER INPUTS)
BURST FLAG/
MODULATOR
RIN/GIN BIN
RESTORE
CLAMPS
INPUT
Y
C
Description
Input valid sync width for burst
insertion (user-controlled).
Minimum sync to color delay
(user-controlled).
Delay to modulator clamp start.
Length of modulator offset clamp
(no chroma during this period).
Delay to input clamping start.
Length of input clamp (no RGB
response during this period).
Delay to start of delay line
clock reset.
Length of delay line clock reset
(no luma response during this
period), also burst gate.
Delay from sync input assertion
to sync in LUMA output.
Delay from RGB input assertion
to LUMA output response.
Delay from valid horizontal sync
start to CRMA colorburst output.
Delay from RGB input assertion
to CRMA output response.
t
SS
t
Table I. Timing Description (See Figure 6)
SW
t
t
SR
SD
t
SC
t
SM
t
SB
t
t
RW
DW
t
MW
Min
Max
Min
Typ
Typ
Typ
Typ
t
BC
NTSC
t
BY
1
2.8 µs
5.3 µs
8.2 µs
8.4 µs
1.1 µs
5.4 ms
2.5 µs
5.7 µs
2.5 µs
310 ns
340 ns
5.8 µs
360 ns
Min
Max
Min
Typ
Typ
Typ
Typ
PAL
2
3.3 µs
5.4 µs
8.1 µs
8.3 µs
0.9 µs
5.6 ms
2.3 µs
5.8 µs
2.3 µs
265 ns
280 ns
5.9 µs
300 ns