ADMC331-PB Analog Devices, ADMC331-PB Datasheet
ADMC331-PB
Related parts for ADMC331-PB
ADMC331-PB Summary of contents
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... PROGRAM MEMORY ADDRESS DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA SERIAL PORTS TIMER SPORT 0 SPORT 1 SHIFTER Single Chip DSP Motor Controller ADMC331 PWMTRIP (Continued on page 7) WATCH- 24-BIT DOG PIO TIMER 7 16-BIT 2 8 BIT ANALOG 3-PHASE AUX PWM ...
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... ADMC331–SPECIFICATIONS Parameter ANALOG-TO-DIGITAL CONVERTER Signal Input Resolution Converter Linearity Zero Offset Channel-to-Channel Comparator Match Comparator Delay Current Source Current Source Linearity ELECTRICAL CHARACTERISTICS V Logic Low IL V Logic High IH V Low Level Output Voltage OL V Low Level Output Voltage (XTAL) ...
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... TIMING PARAMETERS Parameter Clock Signals t is defined as 0 The ADMC331 uses an input clock with a frequency equal CK CKI to half the instruction rate MHz input clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor cycle (equivalent to 26 MHz 0.5 t period should be substituted for all relevant timing parameters to obtain CKI specification value ...
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... ADMC331 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...
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... Range ADMC331BST –40°C to +85°C ADMC331-ADVEVALKIT ADMC331-PB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADMC331 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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... GND GND 56 I/P BIDIR PIO17 57 I/P GND GND 58 BIDIR BIDIR PIO18 59 O/P GND GND 60 I/P PIN CONFIGURATION 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) PIN 1 IDENTIFIER ADMC331 TOP VIEW (Not to Scale) Pin Pin Pin Pin Name No. Type Name GND 61 BIDIR TFS0 GND 62 BIDIR RFS0 XTAL 63 I/P DR0 ...
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... The ADMC331 integrates a 26 MIPS, fixed-point DSP core with a complete set of motor control peripherals that per- mits fast, efficient development of motor controllers. The DSP core of the ADMC331 is the ADSP-2171, which is completely code compatible with the ADSP-2100 DSP family and combines three computational units, data address genera- tors and a program sequencer ...
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... The sequencer supports conditional jumps and subroutine calls and returns in a single cycle. With internal loop counters and loop stacks, the ADMC331 executes looped code with zero overhead; no explicit jump instructions are required to maintain the loop. ...
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... When it reads data (not instructions) from 24-bit program memory to a 16-bit data register, the lower eight bits are placed in the PX register. The ADMC331 can respond to a number of distinct DSP core and peripheral interrupts. The DSP core interrupts include serial port receive and transmit interrupts, timer interrupts, software interrupts and external interrupts ...
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... ADMC331. In the inter- active mode, the host can access both the internal DSP and periph- eral motor control registers of the ADMC331, read and write to both program and data memory, implement breakpoints and per- form single-step and run/halt operation as part of the program debugging cycle ...
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... SCLK1 RESET RFS1/ SROM Clock Signals The ADMC331 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation nor operated below the specified minimum frequency during normal operation external clock is used, it should be a TTL-compatible signal running at half the instruction rate ...
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... ADMC331, this register must always contain the value 0x8000 (which is the default). The configuration of both the SYSCNTL and MEMWAIT registers of the ADMC331 is shown at the end of the data sheet. THREE-PHASE PWM CONTROLLER Overview The PWM generator block of the ADMC331 is a flexible, pro- ...
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... DSP clock. In addition to the hardware shutdown fea- ture, the PWM system may be shutdown in software by writing to the PWMSWT register. Status information about the PWM system of the ADMC331 is available to the user in the SYSSTAT register. In particular, the state of the PWMTRIP, PWMPOL and PWMSR pins is available, as well as a status bit that indicates whether operation is in the first half or the second half of the PWM period ...
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... CLKOUT rate of 26 MHz. Obviously, the deadtime can be programmed to be zero by writing 0 to the PWMDT register. PWM Operating Mode, MODECTRL and SYSSTAT Registers The PWM controller of the ADMC331 can operate in two distinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register ...
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... Width of the PWMSYNC Pulse, PWMSYNCWT Register The PWM controller of the ADMC331 produces an output PWM synchronization pulse at a rate equal to the PWM switch- ing frequency in single update mode and at twice the PWM frequency in the double update mode. This pulse is available for external use at the PWMSYNC pin. The width of this PWMSYNC pulse is programmable by the 8-bit read/write PWMSYNCWT register ...
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... CK be turned ON for the entire half period (100% duty cycle). Switched Reluctance Mode The PWM block of the ADMC331 contains a switched reluc- tance mode that is controlled by the state of the PWMSR pin. The switched reluctance (SR) mode is enabled by connecting the PWMSR pin to GND. In this SR mode, the low side PWM ...
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... The chopped active PWM signals may be required for the high side drivers only, for the low side drivers only or for both the high side and low side switches. Therefore, indepen- dent control of this mode for both high and low side switches is ADMC331 PWMCHA PWMCHA = PWMCHB ...
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... PWMSYNC boundary. PWM Registers The configuration of the PWM registers is described at the end of the data sheet. ADC OVERVIEW The Analog Input Block of the ADMC331 is a 7-channel single 2 PWMDT slope Analog Data Acquisition System with 12-bit resolution. Data Conversion is performed by timing the crossover between the Analog Input and Sawtooth Reference Ramp ...
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... For a given capacitance value, C ADCAUX NOM CLKOUT where I CONST T is the PWMSYNC pulsewidth. In selecting the capacitor CRST value, however necessary to take into account the tolerance of the capacitor and the variation of the current source value. ADMC331 CMAX t VIL T CRST T – T PWM ...
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... PWM out- put signals can be used as simple single-bit digital-to-analog converters. The auxiliary PWM system of the ADMC331 can operate in two different modes, independent mode or offset mode. The operating mode of the auxiliary PWM system is controlled by Bit 8 of the MODECTRL register ...
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... DSP core and motor control peripheral reset is performed. In addition, Bit 1 of the SYSSTAT register is set so that after a watchdog reset the ADMC331 can determine that the reset was due to the timeout of the watchdog timer and not an external reset. Following a watchdog reset, Bit 1 of the SYSSTAT register may be cleared by writing zero to the WDTIMER register ...
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... If any peripheral interrupt enabled, the IRQ2 interrupt enable bit (Bit 9) of the IMASK register must be set. The configuration of the IMASK register of the ADMC331 is shown at the end of the data sheet. Interrupt Configuration The IFC and ICNTL registers of the DSP core control and configure the interrupt controller of the DSP core ...
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... The monitor code in ROM automatically configures the SPORT1 pins during the boot sequence. Initially, the DR1SEL bit is cleared and the UARTEN bit is set so that the ADMC331 first attempts to perform a reset of the external memory device using the RFS1/SROM pin. This is accomplished by toggling the FL1 flag using the following code segment: SROMRESET: SET FL1 ...
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... ADMC331 Address Offset (HEX) (Decimal) 0x2000 0 0x2001 1 0x2002 2 0x2003 3 0x2004 4 0x2005 5 0x2006 6 0x2007 7 0x2008 8 0x2009 9 0x200A 10 0x200B 11 0x200C 12 0x200D 13 0x200E 14 0x200F 15 0x2010 16 0x2011 17 0x2012 18 0x2013 19 0x2014 20 0x2015 21 0x2016 22 0x2017 23 0x2018 24 0x2019 . . . 0x2040 . . . 0x2044 68 0x2045 69 0x2046 70 0x2047 71 0x2048 72 0x2049 73 0x204A ...
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... SPORT0 Control Register [ SPORT0 Clock Divide Register [ SPORT0 Receive Frame Sync Divide [ SPORT0 Autobuffer Control Register [ SPORT1 Control Register [ SPORT1 Clock Divide Register [ SPORT1 Receive Frame Sync Divide [ SPORT1 Autobuffer Control Register ADMC331 ...
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... Bit 1 indicates that a PWMSYNC interrupt has occurred. Register Memory Map The address, name, used bits and function of all motor control peripheral registers of the ADMC331 are tabulated in Table X. In addition, the relevant DSP core registers are tabulated in Table XI. Full details of the DSP core registers can be obtained by referring to the ADSP-2171 sections of the ADSP-2100 Family User’ ...
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... PWMSWT (R/ ADMC331 (0x2008) PWMTM f CLKOUT f = PWM 2 PWMTM (0x2009 PWMDT 2 PWMDT SECONDS CLKOUT (0x200F ...
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... ADMC331 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING PWMPD (R/ PWMGATE (R/ PWMCHA (R/ ...
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... PIODATA1 (R/ PIODATA2 (R/ ADMC331 (0x2004 INPUT 1 = OUTPUT (0x2044 INPUT 1 = OUTPUT (0x2048 INPUT 1 = OUTPUT ...
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... ADMC331 PIOINTEN0 (R/ PIOINTEN1 (R/ PIOINTEN2 (R/ ...
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... AUXTM1 (R/ ADMC331 (0x2010 (AUXCH0) t ON, AUX0 (0x2011 (AUXCH1) t ON, AUX1 (0x2012 AUX0 PERIOD = 2 ...
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... ADMC331 ADC1 ( ADC2 ( ADC3 ( ADCAUX ( (0x2000 ...
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... WDTIMER ( ADMC331 (0x2015 ADC MUX CONTROL 00 VAUX0 01 VAUX1 10 VAUX2 11 VAUX3 PWMTRIP 0 = DISABLE INTERRUPT 1 = ENABLE PWMSYNC 0 = DISABLE INTERRUPT 1 = ENABLE SPORT1 DATA 0 = DR1A ...
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... ADMC331 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SPORT0 TRANSMIT SPORT0 RECEIVE SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2) RESERVED (SET DISABLE SPORT0 TRANSMIT (MASK ENABLE SPORT0 RECEIVE SOFTWARE 1 ICNTL ...
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... ENABLED SYSCNTL (R/ FI, FO, IRQ0, IRQ1, SCLK SPORT1 CONFIGURE 1 = SERIAL PORT MEMWAIT (R/ ADMC331 DM (0x3FFF) DM (0x3FFE) ...
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... ADMC331 0.030 (0.75) 0.020 (0.50) 0.006 (0.15) 0.002 (0.05) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead Plastic Thin Quad Flatpack (TQFP) (ST-80) 0.640 (16.25) 0.620 (15.75) 0.553 (14.05) 0.063 (1.60) MAX 0.549 (13.95) 0.486 (12.35) TYP SEATING PLANE TOP VIEW (PINS DOWN) 0.004 20 (0.10 MAX 0.029 (0.73) 0.014 (0.35) 0.010 (0.25) 0.022 (0.57) 0.057 (1.45) 0.053 (1.35) ...