ADMC331-PB Analog Devices, ADMC331-PB Datasheet - Page 17

• Manufacturer Part Number: ADMC331-PB
• Description: Single Chip DSP Motor Controller
• Manufacturer: Analog Devices

PWMSR
The SR mode can only be enabled by connecting the PWMSR
pin to GND. There is no software means by which this mode
can be enabled. There is an internal pull-up resistor on the
PWMSR pin so that if this pin is left unconnected or becomes
disconnected the SR mode is disabled. Of course, the SR mode
is disabled when the PWMSR pin is tied to V
the PWMSR pin may be read from Bit 4 of the SYSSTAT
register.
Output Control Unit, PWMSEG Register
The operation of the Output Control Unit is controlled by the
9-bit read/write PWMSEG register that controls two distinct
features that are directly useful in the control of ECM or BDCM.
The PWMSEG register contains three crossover bits, one for
each pair of PWM outputs. Setting Bit 8 of the PWMSEG
register enables the crossover mode for the AH/AL pair of PWM
signals; setting Bit 7 enables crossover on the BH/BL pair of
PWM signals; setting Bit 6 enables crossover on the CH/CL
pair of PWM signals. If crossover mode is enabled for any pair
of PWM signals, the high side PWM signal from the timing unit
(i.e. AH) is diverted to the associated low side output of the
Output Control Unit so that the signal will ultimately appear at
the AL pin. Of course, the corresponding low side output of the
Timing Unit is also diverted to the complementary high side
output of the Output Control Unit so that the signal appears at
the AH pin. Following a reset, the three crossover bits are
cleared so that the crossover mode is disabled on all three pairs
of PWM signals.
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six
PWM outputs. The PWM signal of the AL pin is enabled by
setting Bit 5 of the PWMSEG register while Bit 4 controls AH,
Bit 3 controls BL, Bit 2 controls BH, Bit 1 controls CL and
Bit 0 controls the CH output. If the associated bit of the
PWMSEG register is set, then the corresponding PWM output
is disabled irrespective of the value of the corresponding duty
cycle register. This PWM output signal will remain in the OFF
state as long as the corresponding enable/disable bit of the
PWMSEG register is set. The implementation of this output
enable function is implemented after the crossover function.
Following a reset, all six enable bits of the PWMSEG register
are cleared so that all PWM outputs are enabled by default.
AH
BH
CH
AL
BL
CL
PWMTM
PWMCHC
PWMCHB
1
1
PWMCHA
1
1
PWMCHB
PWMCHC
PWMCHA
PWMTM
2
2
DD
2
2
. The state of
In a manner identical to the duty-cycle registers, the PWMSEG
is latched on the rising edge of the PWMSYNC signal so that
the changes to this register only become effective at the start of
each PWM cycle in single update mode. In double update mode,
the PWMSEG register can also be updated at the midpoint of
the PWM cycle.
In the control of an ECM, only two inverter legs are switched
at any time and often the high side device in one leg must be
switched ON at the same time as the low side driver in a second
leg. Therefore, by programming identical duty cycles values for
two PWM channels (i.e., PWMCHA = PWMCHB) and setting
Bit 7 of the PWMSEG register to crossover the BH/BL pair if
PWM signals, it is possible to turn ON the high side switch of
phase A and the low side switch of Phase B at the same time.
In the control of ECM, it is usual that the third inverter leg
(Phase C in this example) be permanently disabled for a number
of PWM cycles. This function is implemented by disabling both
the CH and CL PWM outputs by setting Bits 0 and 1 of the
PWMSEG register. This situation is illustrated in Figure 9
where it can be seen that both the AH and BL signals are identi-
cal, since PWMCHA = PWMCHB and the crossover bit for
Phase B is set. In addition, the other four signals (AL, BH, CH
and CL) have been disabled by setting the appropriate enable/
disable bits of the PWMSEG register. For the situation illus-
trated in Figure 9, the appropriate value for the PWMSEG
register is 0x00A7. In normal ECM operation, each inverter leg
is disabled for certain periods of time, so that the PWMSEG
register is changed based on the position of the rotor shaft
(motor commutation).
Gate Drive Unit, PWMGATE Register
The Gate Drive Unit of the PWM controller adds features
that simplify the design of isolated gate drive circuits for
PWM inverters. If a transformer-coupled power device gate
driver amplifier is used, the active PWM signals must be
chopped at a high frequency. The 10-bit read/write PWMGATE
register allows the programming of this high frequency chopping
mode. The chopped active PWM signals may be required for
the high side drivers only, for the low side drivers only or for
both the high side and low side switches. Therefore, indepen-
dent control of this mode for both high and low side switches is
AH
BH
CH
AL
BL
CL
2
PWMDT
PWMTM
PWMCHA
= PWMCHB
PWMCHA
= PWMCHB
PWMTM
ADMC331
2
PWMDT