UPD70208HGF-16-3B9 NEC, UPD70208HGF-16-3B9 Datasheet - Page 34

• Manufacturer Part Number: UPD70208HGF-16-3B9
• Description: V40HLTM/ V50HLTM 16/8/ 16-BIT MICROPROCESSOR
• Manufacturer: NEC

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13. STANDBY FUNCTIONS
14. RESET OPERATION
and on-chip peripheral LSIs are reset.
FFFF0H.
area.
(1) HALT mode
(2) STOP mode
The V40HL and V50HL have two modes, the HALT mode and STOP mode, as standby functions.
Remark Switching between HALT mode and STOP mode is performed by setting a system I/O area register.
When the RESET pin is driven low and this level is held for 4 clock cycles or more from the fall of the signal, the CPU
When the RESET pin subsequently returns to the high level, the CPU begins an instruction prefetch from address
When the V40HL and V50HL are reset, its status is fully compatible with the V40 and V50.
Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved
Table 14-1 shows the main statuses of the on-chip peripheral LSIs when a reset is performed.
When the HALT instruction is executed, the clock to internal CPU circuitry (excluding the HALT mode release circuit)
is stopped.
When the HALT instruction is executed, all clocks to the CPU and internal I/Os are stopped.
STOP mode should be used when a resonator is connected to the X1 and X2 pins.
Caution When a reset is performed, the SCU, TCU, ICU and DMAU cannot be used.
Table 14-1. Main Statuses of On-Chip Peripheral LSIs After Reset
WCU
REFU
SCU
DMAU
Memory, external I/O, DMA & refresh
Upper & lower memory blocks
Refresh cycle
Refresh enabling/disabling
Baud rate
Character
Parity
Stop bits
Break detection : None
Demand mode
Auto initialization disabled
Verify transfer, byte transfer
Bus release mode
DMA enabled
PD71071 mode
Data Sheet U13225EJ4V0DS00
: x 64
: 7 bits
: None
: 1 bit
: set to 72 clock cycles
: not affected by reset
: 3-wait insertion
: set to 512 KB
PD70208H, 70216H