UPD70208HGF-16-3B9 NEC, UPD70208HGF-16-3B9 Datasheet - Page 73

• Manufacturer Part Number: UPD70208HGF-16-3B9
• Description: V40HLTM/ V50HLTM 16/8/ 16-BIT MICROPROCESSOR
• Manufacturer: NEC

(2)
TOUT1
TCTL2 setup time (vs. CLKOUT )
TCTL2 setup time (vs. TCLK )
TCTL2 hold time (vs. CLKOUT )
TCTL2 hold time (vs. TCLK )
TCTL2 high-level width
TCTL2 low-level width
TOUT output delay time (vs. CLKOUT )
TOUT output delay time (vs. TCLK )
TOUT output delay time (vs. TCTL2 )
TCLK rise time
TCLK fall time
TCLK high-level width
TCLK low-level width
TCLK cycle
Access interval
REFRQ
RESET pulse width
Notes 1. This rating is to guarantee the read/write recovery time for the I/O device.
PD70208H, 70216H-20 (T
delay time (vs. MRD )
2. This rating is to guarantee that REFRQ
3. When using internal clock generator by connecting a resonator to the X1 and X2 pins, the oscillation
TxD delay time
bit of the STCL register is 0.
stabilization time must be added at power-ON. Because the oscillation stabilization time varies depending
on the characteristics of the resonator and oscillator used, evaluate the oscillation stabilization time with the
resonator and oscillator actually used.
Note 1
Note 3
Note 2
A
= –40 to +85 C, V
Parameter
Data Sheet U13225EJ4V0DS00
DD
= 5 V 5%) (3/3)
is always behind MRD , and guaranteed only when the EREF
Output Pin Load Capacitance: C
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Symbol
PD70208H, 70216H
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DTX
SGK
SGTK
HKG
HTKG
GGH
GGL
DKTO
DTKTO
DGTO
TKR
TKF
TKTKH
TKTKL
CYTK
AI
DRQHRH
WRESL
2t
t
KKL
PD70208H-20
PD70216H-20
MIN.
CYK
4t
40
40
80
40
40
40
23
23
50
CYK
–10
–15
MAX.
200
150
100
DC
90
25
25
L
= 100 pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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