S29GL128S SPANSION [SPANSION], S29GL128S Datasheet - Page 66

• Manufacturer Part Number: S29GL128S
• Manufacturer: SPANSION [SPANSION]

7.4
7.5
66
Ready/Busy# (RY/BY#)
Hardware Reset
RY/BY# is a dedicated, open drain output pin that indicates whether an Embedded Algorithm, Power-On
Reset (POR), or Hardware Reset is in progress or complete. The RY/BY# status is valid after the rising edge
of the final WE# pulse in a command sequence, when V
falling edge of RESET#. Since RY/BY# is an open drain output, several RY/BY# pins can be tied together in
parallel with a pull up resistor to V
If the output is Low (Busy), the device is actively erasing, programming, or resetting. (This includes
programming in the Erase Suspend mode). If the output is High (Ready), the device is ready to read data
(including during the Erase Suspend mode), or is in the standby mode.
Table 5.3, Data Polling Status on page 42
If an Embedded algorithm has failed (Program / Erase failure as result of max pulses or Sector is locked),
RY/BY# will stay Low (busy) until status register bits 4 and 5 are cleared and the reset command is issued.
This includes Erase or Programming on a locked sector.
The RESET# input provides a hardware method of resetting the device to standby state. When RESET# is
driven Low for at least a period of t
 terminates any operation in progress,
 exits any ASO,
 tristates all outputs,
 resets the Status Register,
 resets the EAC to standby state.
 CE# is ignored for the duration of the reset operation (t
 To meet the Reset current specification (I
To ensure data integrity any operation that was interrupted should be reinitiated once the device is ready to
accept another command sequence.
IO
GL-S MirrorBit
RP
.
, the device immediately:
shows the outputs for RY/BY# in each operation.
CC5
D a t a
) CE# must be held High.
®
Family
S h e e t
CC
RPH
is above V
).
S29GL_128S_01GS_00_06 March 16, 2012
CC
minimum during POR, or after the