S29PL-N SPANSION [SPANSION], S29PL-N Datasheet - Page 75

• Manufacturer Part Number: S29PL-N
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

12 Appendix
November 23, 2005 S29PL-N_00_A4
Read (7)
Reset (8)
Program
Write to Buffer (17)
Program Buffer to Flash
Write to Buffer Abort Reset (17)
Chip Erase
Sector Erase
Program/Erase Suspend (14)
Program/Erase Resume (15)
CFI Query (16)
Secured Silicon Sector Command Definitions
Legend:
X = Don’t care.
RA = Read Address.
RD = Read Data.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse whichever
happens later.
PD = Program Data. Data latches on the rising edge of WE# or CE#
pulse, whichever occurs first.
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Secured
Bypass
Unlock
Silicon
Sector
Auto-
select
Mode
(9)
See
All values are in hexadecimal.
Except for the following, all bus cycles are write cycle: read
cycle, fourth through sixth cycles of the Autoselect commands,
fourth cycle of the password verify command, and any cycle
reading at RD(0) and RD(1).
Data bits DQ15 – DQ8 are don’t care in command sequences,
except for RD, PD, WD, PWD, and PWD3 – PWD0.
Unless otherwise noted, these address bits are don’t cares:
PL127: A22 – A15; 129N: A21 – A15; PL256N: A23 – A14.
Writing incorrect address and data values or writing them in the
improper sequence may place the device in an unknown state.
The system must write the reset command to return the device
to reading array data.
No unlock or command cycles required when bank is reading
array data.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information) or
performing sector lock/unlock.
(Table
Manufacturer ID
Device ID (10)
Indicator Bits
Unlock Bypass Entry
Unlock Bypass Program (12, 13)
Unlock Bypass Sector Erase (12, 13) 2
Unlock Bypass Erase (12, 13)
Unlock Bypass CFI (12, 13)
Unlock Bypass Reset
Secured Silicon Sector Entry (18)
Secured Silicon Sector Program
Secured Silicon Sector Read
Secured Silicon Sector Exit (19)
Command Sequence
7.1) for description of bus operations.
This section contains information relating to software control or interfacing with the Flash device.
For additional information and assistance regarding software, see
plore the Web at
(Notes)
www.amd.com
P r e l i m i n a r y
Table 12.1 Memory Array Commands
1
1
4
6
4
4
6
1
3
6
6
1
1
1 [BA]555
3
2
2
1
2
3
2
1
4
S29PL-N MirrorBit™ Flash Family
Addr
XXX
555
555
555
555
555
555
555
555
555
555
555
RA
SA
BA
BA
XX
XX
XX
BA
XX
XX
RA
First
Data Addr Data
data
RD
AA
AA
AA
AA
AA
AA
and www.fujitsu.com.
F0
AA
AA
AA
29
AA
B0
30
98
AA
A0
80
80
98
90
A0
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
XXX
XXX
2AA
2AA
PA
SA
PA
Second
data
PD
55
55
55
55
55
55
55
55
55
30
10
00
55
55
SA = Sector Address. PL127/129N = A22 – A15;
PL256N = A23 – A15.
BA = Bank Address. PL256N = A23 – A21; PL127N = A22 – A20;
PL127N = A21 – A20.
WBL = Write Buffer Location. Address must be within the same write
buffer page as PA.
WC = Word Count. Number of write buffer locations to load minus 1.
9.
10. Device IDs: PL256N = 223Ch; PL127N = 2220h;
11. See Autoselect.
12. The Unlock Bypass command sequence is required prior to this
13. The Unlock Bypass Reset command is required to return to
14. The system may read and program in non-erasing sectors, or
15. The Erase Resume command is valid only during the Erase
16. The total number of cycles in the command sequence is
The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address. See
Autoselect.
PL129N = 2221h.
command sequence.
reading array data when the bank is in the unlock bypass mode.
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
Suspend mode, and requires the bank address.
determined by the number of words written to the write buffer.
The maximum number of cycles in the command sequence is 37.
[BA]555
[BA]555
[BA]555
Addr
555
555
555
555
555
555
555
SA
Third
Bus Cycles (Notes
Data
90
90
90
A0
25
80
80
20
88
90
F0
[BA]X00 0001
[BA]X01 227E [BA]X0E
[BA]X03
Addr
555
555
SA
XX
PA
Fourth
1
(Note
Data
Data
11)
WC
– 6)
AA
AA
00
Additional
Addr
2AA
2AA
PA
Fifth
(Note
Resources, or ex-
Data
10)
PD
55
55
[BA]X0F 2200
Addr
WBL
555
SA
Sixth
Data
PD
10
30
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