S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet
S29PL-N_07
Related parts for S29PL-N_07
S29PL-N_07 Summary of contents
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... Data Sheet (Preliminary) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29PL-N_00 ™ Flash Family Notice On Data Sheet Designations Revision A Amendment 5 ™ ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO ™ S29PL-N MirrorBit Flash Family S29PL-N_00_A5 June 6, 2007 ...
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... The S29PL129N device offers the additional feature of dual chip enable inputs (CE1# and CE2#) that allow each half of the memory space to be controlled separately. ...
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... Typical Program & Erase Times (typical values) , 10,000 cycles; checkerboard data pattern. CC Package Options VBH064 8.0 x 11.6 mm, 64-ball ™ S29PL-N MirrorBit Flash Family µA (See Note) 40 µs 9.4 µs 6 µs 300 ms 1.6 s VBH084 8.0 x 11.6 mm, 84-ball S29PL-N_00_A5 June 6, 2007 ...
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... Secured Silicon Sector Entry and Exit Command Sequences 11. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.6 V Power 11.7 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11.8 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 June 6, 2007 S29PL-N_00_A5 ™ S29PL-N MirrorBit Flash Family 5 ...
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... Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13. Common Flash Memory Interface 14. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ™ S29PL-N MirrorBit Flash Family S29PL-N_00_A5 June 6, 2007 ...
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... Write Buffer Programming Operation Figure 7.3 Sector Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7.4 Write Operation Status Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 7.5 Simultaneous Operation Block Diagram for S29PL256N and S29PL127N . . . . . . . . . . . . . . 41 Figure 7.6 Simultaneous Operation Block Diagram for S29PL129N . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 8.1 Advanced Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 8.2 Lock Register Program Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 11.1 Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 11.2 Maximum Positive Overshoot Waveform ...
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... Table 12.2 Sector Protection Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 13.1 CFI Query Identification String Table 13.2 System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 13.3 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 13.4 Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ™ S29PL-N MirrorBit Flash Family S29PL-N_00_A5 June 6, 2007 ...
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... Process Technology N = 110 nm MirrorBit™ Technology Flash Density 256= 256 Mb 129= 128 Mb (Dual CE#) 127= 128 Mb (Single CE#) Product Family S29PL = 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory Valid Combinations Package Type, Material, Model Packing & Temperature Range Number Type ...
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... IH When RY/BY the device is either executing an embedded algorithm or the device is OL executing a hardware reset operation. Device Power Supply Hardware reset pin Chip Enable inputs for S29PL129 device Figure 2.1 Logic Symbols – PL256N, PL129N, and PL127N 16 DQ15 – DQ0 RY/BY# ™ S29PL-N MirrorBit Flash Family Description Logic Symbol – ...
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... A2–A0 Notes 1. RY/BY open drain output A23 (PL256N), A22 (PL127N), A21 (PL129N). max 3. PL129N has two CE# pins CE1# and CE2#. June 6, 2007 S29PL-N_00_A5 Sector Switches Erase Voltage Generator PGM Voltage Generator Timer ™ ...
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... Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. 4.2 VBH084, 8.0 x 11.6 mm 4.2.1 Connection Diagram – S29PL256N MCP Compatible Package Figure 4.1 Connection Diagram – 84-ball Fine-Pitch Ball Grid Array (S29PL256N RFU C2 RFU ...
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... 4.2.2 Physical Dimensions – VBH084, 8.0 x 11.6 mm Figure 4.2 Physical Dimensions – 84-ball Fine-Pitch Ball Grid Array (S29PL256N) 0.05 C (2X) A1 CORNER INDEX MARK PACKAGE VBH 084 JEDEC N/A 11. 8.00 mm NOM PACKAGE SYMBOL MIN NOM A --- --- A1 0.18 --- A2 0.62 --- D 11.60 BSC. E 8.00 BSC. D1 8.80 BSC. E1 7.20 BSC φ ...
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... VBH064 11.6 mm 4.3.1 Connection Diagram – S29PL127N MCP Compatible Package Figure 4.3 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL127N CE1# J2 RFU M1 NC Notes 1. Top view—balls facing down. 2. Recommended for wireless applications ...
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... 4.3.2 Connection Diagram – S29PL129N MCP Compatible Package Figure 4.4 Connection Diagram – 64-Ball Fine-Pitch Ball Grid Array (S29PL129N CE1# J2 RFU M1 NC Notes 1. Top view—balls facing down. 2. Recommended for wireless applications June 6, 2007 S29PL-N_00_A5 ...
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... Physical Dimensions – VBH064 11.6 mm – S29PL-N Figure 4.5 Physical Dimensions – 64-Ball Fine-Pitch Ball Grid Array (S29PL-N) 0.05 C (2X) A1 CORNER INDEX MARK A A1 PACKAGE VBH 064 JEDEC 11. 8.00 mm NOM PACKAGE SYMBOL MIN NOM A --- A1 0.18 A2 0.62 D 11.60 BSC. E 8.00 BSC. D1 8.80 BSC. E1 7.20 BSC φb 0.33 e 0.80 BSC. ...
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... Sunnyvale, CA 94088-3453, USA Telephone: 408-962-2500 or 1-866-SPANSION Spansion Japan Limited 4-33-4 Nishi Shinjuku, Shinjuku-ku Tokyo, 160-0023 Telephone: +81-3-5302-2200 Facsimile: +81-3-5302-2674 http://www.spansion.com June 6, 2007 S29PL-N_00_A5 obtain the following related documents: ™ S29PL-N MirrorBit Flash Family 17 ...
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... Product Overview The S29PL-N family consists of 256 and 128 Mb, 3.0 volts-only, simultaneous read/write page-mode read Flash devices that are optimized for wireless designs of today that demand large storage array and rich functionality, while requiring low power consumption. These products also offer 32-word buffer for programming with program and erase suspend/resume functionality ...
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... Size Count June 6, 2007 S29PL-N_00_A5 Table 6.2 PL127N Sector and Memory Address Map Sector Size Sector/ (KB) Sector Range Address Range 64 SA00 000000h-007FFFh 64 SA01 008000h-00FFFFh 64 SA02 ...
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... Data Out OUT ™ S29PL-N MirrorBit Flash Family Table 12.2 on page 68). The command register describes the required state of each Addresses WP#/ACC (A – A0) DQ15 – DQ0 max (See Note High High High-Z IN S29PL-N_00_A5 June 6, 2007 OUT IN ...
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... CE output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming the addresses have been stable for at least t June 6, 2007 S29PL-N_00_A5 for the PL129N Sector and Memory Address Map. ...
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... Word 1 0 Word 2 0 Word 3 0 Word 4 1 Word 5 1 Word 6 1 Word 7 1 ™ S29PL-N MirrorBit Flash Family . When CE# is deasserted (= V ), the Here again, CE# selects the device ACC S29PL-N_00_A5 June 6, 2007 ...
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... H = Logic High = Bank Address SA = Sector Address Note For the PL129N either CE1# or CE2# must be low to access Autoselect Codes June 6, 2007 S29PL-N_00_A5 for command sequence details. Table 7.4 Autoselect Codes –A12 A10 A9 A8 ...
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... Table 7.5 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) Operation Word Address Write BAx555h Write BAx2AAh Write BAx555h Table 7.6 Autoselect Exit (LLD Function = lld_AutoselectExitCmd) Operation Word Address Write base + xxxh ™ S29PL-N MirrorBit Flash Family Data 0x00AAh 0x0055h 0x0090h Data 0x00F0h S29PL-N_00_A5 June 6, 2007 ...
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... Single word programming is supported for backward compatibility with existing Flash driver software and use of write buffer programming is strongly recommended for general programming. The effective word programming time using write buffer programming is approximately four times faster than the single word programming time. June 6, 2007 S29PL-N_00_A5 Table 7.1 on page 20 for information on these status bits ...
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... S29PL-N MirrorBit Flash Family Unlock Cycle 1 Unlock Cycle 2 Setup Command Program Address (PA), Program Data (PD) Error condition (Exceeded Timing Limits) Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 00A0h Word Address Data Word */ */ */ */ S29PL-N_00_A5 June 6, 2007 ...
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... Write buffer programming is approximately four times faster than programming one word at a time. Note that the Secured Silicon, the CFI functions, and the Autoselect Codes are not available for read when a write buffer programming operation is in progress. June 6, 2007 S29PL-N_00_A5 ...
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... S29PL-N MirrorBit Flash Family Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Program Address 0025h Program Address Word Count (N–1)h Program Address, Word N Word N Sector Address 0029h */ */ */ */ */ */ */ */ S29PL-N_00_A5 June 6, 2007 */ */ */ */ */ */ */ */ */ */ */ ...
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... Write Next Word, Decrement wc: PA ≤ data , – 1 RESET. Issue Write Buffer Abort Reset Command June 6, 2007 S29PL-N_00_A5 Figure 7.2 Write Buffer Programming Operation Write Unlock Cycles: Address 555h, Data AAh ...
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... SEA . Any sector erase address and command for information on these status bits. AC Characteristics on page 59 Word Address Base + 555h Base + 2AAh Base + 555h Base + 555h Base + 2AAh Sector Address . SEA */ */ */ */ S29PL-N_00_A5 June 6, 2007 66, and for Data 00AAh 0055h 0080h 00AAh 0055h 0030h ...
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... PASS. Device returns to reading array. Notes 1. See Table 12.1 on page 66 2. See the section on DQ3 for information on the sector erase timeout. June 6, 2007 S29PL-N_00_A5 Figure 7.3 Sector Erase Operation Write Sector Erase Cycles: Command Cycle 1 ...
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... S29PL-N MirrorBit Flash Family 66. These commands invoke the 68) show the address and data Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0080h Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0010h */ */ */ */ S29PL-N_00_A5 June 6, 2007 ...
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... Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase resume command */ *((UINT16 *)bank_addr + 0x000) = 0x0030; /* The flash needs adequate time in the resume state */ June 6, 2007 S29PL-N_00_A5 Table 7.18 on page 40 and Autoselect on page 23 for details ...
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... Table 7.14 Program Resume (LLD Function = lld_ProgramResumeCmd) Operation Write /* write resume command ™ S29PL-N MirrorBit Flash Family for more information. for more information. Word Address Data Bank Address 00B0h Word Address Data Bank Address 0030h S29PL-N_00_A5 June 6, 2007 */ */ ...
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... The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the read mode. June 6, 2007 S29PL-N_00_A5 ...
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... Reset Cycle 2 Write ™ S29PL-N MirrorBit Flash Family Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0020h */ */ */ */ */ */ */ */ Word Address Data Base +xxxh 00A0h Program Address Program Data */ */ Word Address Data Base +xxxh 0090h Base +xxxh 0000h S29PL-N_00_A5 June 6, 2007 ...
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... See the following for more information: Data# Polling on DQ7. algorithm. Figure 11.13, Data# Polling Timings (During Embedded Algorithms) on page 64 Polling timing diagram. June 6, 2007 S29PL-N_00_A5 then the bank returns to the read mode. If not all selected sectors are ASP Table 7 ...
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... S29PL-N MirrorBit Flash Family YES Erase Operation Complete Read 2 Read3= valid data? NO Read 3 Program Operation Failed YES Programming Operation? NO (Note 1) YES DQ6 DEVICE toggling? ERROR NO (Note 2) YES DQ2 toggling? NO Erase Device in Operation Erase/Suspend Complete Mode S29PL-N_00_A5 June 6, 2007 YES (Note 5) ...
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... Alternatively, it can choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. Refer to Status Flowchart on page 38 June 6, 2007 S29PL-N_00_A5 Figure 7.4, Write Operation Status Flowchart on page Figure 11 ...
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... S29PL-N MirrorBit Flash Family DQ1 DQ2 DQ3 (Note 2) (Note 4) INVALID INVALID INVALID (Not Allowed) (Not Allowed) (Not Allowed) Data Data Data N/A Toggle N/A Data Data Data N/A N/A N/A N/A N/A 0 N/A N/A 0 N/A N/A 1 Figure 11.12, Back-to-back S29PL-N_00_A5 June 6, 2007 ...
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... operation with zero latency. See the table, while-erase current specifications. Figure 7.5 Simultaneous Operation Block Diagram for S29PL256N and S29PL127N – A0 max A –A0 max RESET# WE# CE# WP#/ACC DQ0 – DQ15 A – A0 max Note A = A23 (PL256N), A22 (PL127N) max ...
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... Figure 7.6 Simultaneous Operation Block Diagram for S29PL129N A21 – A0 A21 – A0 RESET# WE# CE1# CE2# WP#/ACC DQ0 – DQ15 A21 – A0 7.6 Writing Commands/Command Sequences During a write operation, the system must drive CE# and WE address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising edge of WE# or CE# ...
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... Abort Reset command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence (see command tables for detail). June 6, 2007 S29PL-N_00_A5 Table 12.1 on page Table 7 ...
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... Flash Family Figure 8.1 on page 44. Lock Register (One Time Programmable) Persistent Method (DQ1) (Notes PPBs Unlocked Dynamic Protection Bit (DYB) 6) (Notes DYB 0 DYB 1 DYB 2 DYB N-2 DYB N-1 DYB Sector Unprotected. corresponding PPB is 1 (unprotected). (see ordering options). S29PL-N_00_A5 June 6, 2007 ...
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... Dynamically locked. The selected sectors are protected and can be altered via software commands. 3. Unlocked. The sectors are unprotected and can be erased and/or programmed. These states are controlled by the bit types described in Sections June 6, 2007 S29PL-N_00_A5 Table 8.1 Lock Register ...
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... WP have the same function when WP#/ACC = they do when WP#/ACC = V HH ™ S29PL-N MirrorBit Flash Family . Note that the PPB and DYB bits S29PL-N_00_A5 June 6, 2007 ...
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... The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. June 6, 2007 S29PL-N_00_A5 ™ ...
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... S29PL-N MirrorBit Flash Family Lock data may only be progammed once. Sector Protection Status x Protected through PPB x Protected through PPB 1 Unprotected 0 Protected through DYB x Protected through PPB x Protected through PPB 0 Protected through DYB 1 Unprotected Figure 8.1 S29PL-N_00_A5 June 6, 2007 ...
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... Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. 8.7.4 Power-Up Write Inhibit If WE# = CE# = RESET rising edge of WE#. The internal state machine is automatically reset to the read mode on powerup. June 6, 2007 S29PL-N_00_A5 the four outermost sectors are locked (device specific). IL ...
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... V, the standby current is greater. , output from the device is disabled. The outputs are placed in the high IH ™ S29PL-N MirrorBit Flash Family ) for read access, before it CE represents the standby current + 20 ns. The automatic sleep ACC ). If RESET# is held at CC4 S29PL-N_00_A5 June 6, 2007 ...
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... ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services. June 6, 2007 S29PL-N_00_A5 Table 10 ...
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... Exit Secured Silicon Sector command sequence, or until power is removed from the device Table 12.1, Memory Array Commands on page for address and data requirements for both command ™ S29PL-N MirrorBit Flash Family 66, S29PL-N_00_A5 June 6, 2007 ...
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... Example: SecSi Sector Exit Command */ *((UINT16 *)base_addr + 0x555) = 0x00AA; *((UINT16 *)base_addr + 0x2AA) = 0x0055; *((UINT16 *)base_addr + 0x555) = 0x0090; *((UINT16 *)base_addr + 0x000) = 0x0000; June 6, 2007 S29PL-N_00_A5 Table 10.2 Secured Silicon Sector Entry (LLD Function = lld_SecSiSectorEntryCmd) Operation ...
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... 0 –0 +4.0 V –0 +4.0V –0 +10.5 V 200 mA to –2.0 V for periods 0.5 V. During voltage transitions outputs may CC ⁄ ACC may overshoot V to 2.0 V for periods S29PL-N_00_A5 June 6, 2007 ...
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... Voltage range of 2.7 – 3.1 V valid for PL-N MCP products. 11.3 Test Conditions Output Load Capacitance, C Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 11.4 Key to Switching Waveforms Waveform June 6, 2007 S29PL-N_00_A5 Figure 11 ...
Page 56
... Input V /2 Measurement Level CC 0.0 V Description V Setup Time CC Time between RESET# high and CE# low . CC Figure 11.5 V Power-Up Diagram CC t VCS V min CC ™ S29PL-N MirrorBit Flash Family V /2 Output CC Test Setup Speed Min 250 Min 200 Read S29PL-N_00_A5 June 6, 2007 Unit µs ns ...
Page 57
... Automatic sleep mode enables the low power mode when addresses remain stable for t 5. Not 100% tested. 6. The data in the table is for V 7. CE1# and CE2# for the PL129N. June 6, 2007 S29PL-N_00_A5 2 3.6 V) ...
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... MHz MHz 6 –0 (6) CC min V – 0.2 CC 2.3 specifications are with typical V =2 ns. Typical sleep mode current is 1 µA. ACC S29PL-N_00_A5 June 6, 2007 Unit ±2 µA ±1 µ µA 500 µA 40 µ 0 0 ...
Page 59
... For 70pf Output Load Capacitance added to the above t 5. CE1# and CE2# for the PL129N. 11.8.2 Read Operation Timing Diagrams Addresses CE# OE# WE# Data RESET# RY/BY June 6, 2007 S29PL-N_00_A5 Description (Notes) Read Toggle and Data# Polling and Table 11.1 on page 55 for test specifications . DF ...
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... PACC PACC Da+1 Da+2 Da+3 Description (See Note) Figure 11.8 Reset Timings ™ S29PL-N MirrorBit Flash Family Aa+4 Aa+5 Aa+6 Aa PACC PACC PACC PACC Da+4 Da+5 Da+6 Da+7 All Speed Options Min 30 Min 200 S29PL-N_00_A5 June 6, 2007 t DF Unit µs ns ...
Page 61
... Not 100% tested program operation timing, addresses are latched on the falling edge of WE#. 3. See Program/Erase Operations on page 25 4. Does not include the preprogramming time. June 6, 2007 S29PL-N_00_A5 Description (Notes) Write Cycle Time (1) ...
Page 62
... A0h is the true data at the program address OUT Figure 11.10 Accelerated Program Timing Diagram IH t VHH ™ S29PL-N MirrorBit Flash Family Read Status Data (last two cycles WHWH1 Status D OUT t t BUSY VHH S29PL-N_00_A5 June 6, 2007 ...
Page 63
... SA = sector address (for Sector Erase Valid Address for reading status data (see Addresses t AS CE# OE# WE# t WPH Data WE# Controlled Write Cycle June 6, 2007 S29PL-N_00_A5 Figure 11.11 Chip/Sector Erase Operation Timings Erase Command Sequence (last two cycles 2AAh SA ...
Page 64
... Suspend Program Erase Erase Suspend Suspend Read Program ™ S29PL-N MirrorBit Flash Family VA Valid Data True True Valid Data Status Data AHT t CEPH Valid Status (stops toggling) Erase Resume Erase Complete Read S29PL-N_00_A5 June 6, 2007 High Z High Z Valid Data Erase ...
Page 65
... Word programming specification is based upon a single word programming operation not utilizing the write buffer. 11.8.6 BGA Ball Capacitance Parameter OUT C IN2 Notes 1. Sampled, not 100% tested. 2. Test conditions T = 25° 1.0 MHz. A June 6, 2007 S29PL-N_00_A5 Device Typ Condition (Note 1) V 1.6 CC 128 Kword ACC 1.6 V 0.3 ...
Page 66
... Flash Family Additional Resources on page 17, or explore 1 – 6) Fourth Fifth Sixth Addr Data Addr Data Addr [BA]X00 0001 [BA]X01 227E [BA]X0E (10) [BA]X0F [BA]X03 (11) PA Data WBL 555 AA 2AA 55 555 555 AA 2AA S29PL-N_00_A5 June 6, 2007 Data 2200 ...
Page 67
... Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for PL256N. 22. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. June 6, 2007 S29PL-N_00_A5 ™ ...
Page 68
... RD( 555 AA 2AA 55 [BA]555 [BA] [BA]SA 01 RD( ™ S29PL-N MirrorBit Flash Family 1 – 6) Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data 03 PWD3 01 PWD1 02 PWD2 03 PWD3 S29PL-N_00_A5 June 6, 2007 Seventh 00 29 ...
Page 69
... If both the Persistent Protection Mode Locking Bit and the password Protection Mode Locking Bit are set a the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode. 27. The Exit command must be issued to reset the device into read mode. Otherwise the device hangs. June 6, 2007 S29PL-N_00_A5 ™ ...
Page 70
... Primary OEM Command Set 0000h 0040h Address for Primary Extended Table 0000h 0000h Alternate OEM Command Set (00h = none exists) 0000h 0000h Address for Alternate OEM Extended Table (00h = none exists) 0000h ™ S29PL-N MirrorBit Flash Family */ */ Description S29PL-N_00_A5 June 6, 2007 ...
Page 71
... June 6, 2007 S29PL-N_00_A5 Table 13.2 System Interface String Data V Min. (write/erase) CC 0027h D7 – D4: volt, D3 – D0: 100 millivolt V Max. (write/erase) ...
Page 72
... Bank 1 Region Information Number of sectors in bank 0018h (PL129N) 0030h (PL256N) 0018h (PL127N) Bank 2 Region Information Number of sectors in bank 0018h (PL129N) 0013h (PL256N) 000Bh (PL127N) Bank 3 Region Information Number of sectors in bank 000Bh (PL129N) ™ S29PL-N MirrorBit Flash Family Description N bytes N µs N µs S29PL-N_00_A5 June 6, 2007 N ...
Page 73
... Initial release Revision A1 (August 8, 2005) Performance Characteristics Updated Package Options MCP Look-Ahead Connection Diagram Corrected pinout Memory Map Added Sector and Memory Address Map for S29PL127N Device Operation Table Added Dual Chip Enable Device Operation Table Updated t V Power Up CC Added V DC Characteristics Updated typical and maximum values ...
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... Spansion LLC in the US and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners ® , the Spansion Logo, MirrorBit ™ S29PL-N MirrorBit Flash Family ® ® ™ ™ ™ , MirrorBit Eclipse , ORNAND , HD-SIM S29PL-N_00_A5 June 6, 2007 ...