S29PL-N_07 SPANSION [SPANSION], S29PL-N_07 Datasheet - Page 21

• Manufacturer Part Number: S29PL-N_07
• Description: 256/128/128 Mb (16/8/8 M x 16-Bit) CMOS, 3.0 Volt-only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

7.2
June 6, 2007 S29PL-N_00_A5
7.1.1
7.2.1
Asynchronous Read
Dual Chip Enable Device Description and Operation (PL129N Only)
Non-Page Random Read
The dual CE# product (PL129N) offers a reduced number of address pins to accommodate processors with a
limited addressable range. This product operates as two separate devices in a single package and requires
the processor to address half of the memory space with one chip enable and the remaining memory space
with a second chip enable. For more details on the addressing features of the Dual CE# device refer to
Table 6.3 on page 19
Dual chip enable products must be setup appropriately for each operation. To place the device into the active
state either CE1# or CE2# must be set to V
must be set to V
Legend
L = Logic Low = V
VID = 11.5–12.5 V
X = Don’t Care
A
D
Notes
1. The sector and sector unprotect functions may also be implemented by programming equipment.
2. WP#/ACC must be high when writing to the upper two and lower two sectors.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for
read access until the command register contents are altered.
Address access time (t
access time (t
output enable access time is the delay from the falling edge of the OE# to valid data at the output (assuming
the addresses have been stable for at least t
Read
Write
Standby
Output Disable
Reset
Temporary Sector Unprotect
(High Voltage)
IN
OUT
= Address In
= Data Out
Operation
D a t a
CE
IL
IH
) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The
.
Table 7.2
S h e e t
for the PL129N Sector and Memory Address Map.
H = Logic High = V
V
SA = Sector Address
D
ACC
HH
IN
= Data In
= 8.5 – 9.5 V
) is equal to the delay from stable addresses to valid output data. The chip enable
describes the required state of each control pin for any particular operation.
S29PL-N MirrorBit
Table 7.2 Dual Chip Enable Device Operation
CE1#
H
H
H
X
X
L
L
L
( P r e l i m i n a r y )
IH
CE2#
H
L
H
L
H
L
X
X
IL
ACC
. To place the device in standby mode, both CE1# and CE2#
OE#
™
H
H
L
X
X
X
Flash Family
– t
OE
WE#
H
X
H
X
X
L
time).
RESET#
V
H
H
H
H
L
ID
WP#/ACC
(Note 2)
X
X
X
X
X
X
Addresses
(A21 – A0)
A
A
A
X
X
X
IN
IN
IN
DQ15 – DQ0
High-Z
High-Z
High-Z
D
D
D
OUT
IN
IN
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