CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet

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... K × 36) 4-Mbit (128 K × 36) CY7C0852V/CY7C0852AV 167 167 4.0 4.0 225 225 • 198 Champion Court • San Jose CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV or LOW on CE for one clock cycle powers down 1 Address Counter and Mask Register for details. 9-Mbit (256 K × 36) CY7C0853V/CY7C0853AV 133 4.7 270 ...

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... Document Number: 38-06070 Rev. *L [1] I/O I/O Control Control True Dual-Ported RAM Array Address Address Decode Decode TMS Reset MRST TDI JTAG Logic TCK CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 9 DQ –DQ 27R 9 DQ –DQ 18R 9 DQ – –DQ 0R Addr. Read ...

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... Switching Waveforms .................................................... 19 Ordering Information ...................................................... 31 256 K × 3.3 V Synchronous CY7C0853V/CY7C0853AV Dual-Port SRAM ................... 31 128 K × 3.3 V Synchronous CY7C0852V/CY7C0852AV Dual-Port SRAM ................... × 3.3 V Synchronous CY7C0851V/CY7C0851AV Dual-Port SRAM ................... 31 Ordering Code Definitions ......................................... 32 Package Diagrams .......................................................... 33 Acronyms ........................................................................ 36 Document Conventions ................................................. 36 Units of Measure ....................................................... 36 Document History Page ................................................. 37 Sales, Solutions, and Legal Information ...

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... M [2] A16L A14L DQ22L DQ18L N DQ24L DQ20L DQ8L DQ6L P DQ23L DQ21L TDO VSS Note 2. For CY7C0851V/CY7C0851AV, pins M1 and M14 are NC. Document Number: 38-06070 Rev. *L Figure 1. 172-ball BGA pinout (Top View DQ13L VDD DQ11L DQ11R VDD DQ14L DQ12L DQ9L DQ9R ...

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... DQ19L VSS VSS DQ19R DQ18L TDI DQ7L DQ2L DQ2R DQ7R DQ6L DQ5L DQ3L DQ0L DQ0R DQ3R VSS DQ4L VDD DQ1L DQ1R VDD CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV DQ13R VSS NC DQ30R DQ32R DQ14R DQ17R DQ29R DQ33R A0R INTR DQ27R DQ31R A1R A17R ...

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... A 13L 40 A 14L [ 15L [ 16L 43 DQ 24L 44 DQ 20L Document Number: 38-06070 Rev. *L Figure 3. 176-pin TQFP pinout (Top View) CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV DQ 132 34R DQ 131 35R NC 130 A 129 0R A 128 1R A 127 2R A 126 3R V 125 ...

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... Power inputs. DD Notes 3. 9M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits. 4. These pins are not available for CY7C0853V/CY7C0853AV device. Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Description . MAX is asserted LOW when the right port writes ...

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... OE is “Don’t Care” for mailbox operation least one of B0, B1, B2 must be LOW. 9. A16x for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF. 10. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW. 11. Counter operation and mask register operation is independent of chip enables. ...

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... A Mask Reset followed by a Counter Reset Notes 12. This section describes the CY7C0852V/CY7C0852AV, which have 17 address bits and a maximum address value of 1FFFF. The CY7C0851V/CY7C0851AV has 16 address bits, register lengths of 16 bits, and a maximum address value of FFFF. 13. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together. ...

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... Counting by Two When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses ...

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... Document Number: 38-06070 Rev. *L Logic Register Counter/ Address Register Load/Increment Mirror Increment Logic Wrap 17 Bit 0 +1 Wrap 1 Detect CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [14] Mask Address RAM Decode Array Counter To Readback and Address Decode 17 Wrap 17 To Counter Page ...

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... CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [15, 16 Mask Register bit Address Counter bit-0 ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C0851V / CY7C0851AV / CY7C0852V / CY7C0852AV / CY7C0853V / CY7C0853AV incorporates an IEEE 1149.1 serial [17] boundary scan test access port (TAP). The TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1-compliant TAPs. The TAP operates using JEDEC-standard 3 ...

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... Typ Max Min = Min –4.0 mA) 2.4 – Min +4.0 mA) – – 2.0 – – – –10 – –10 – –0.1 – CY7C0851V / – 225 CY7C0851AV / CY7C0852V / CY7C0852AV CY7C0853V / – – CY7C0853AV – 90 MAX – 160 – 55 – 160 CY7C0853V / – – CY7C0853AV ...

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... Capacitance [22] Part Number Parameter CY7C0851V / CY7C0851AV / C IN CY7C0852V / CY7C0852AV C OUT CY7C0853V / CY7C0853AV OUT AC Test Load and Waveforms Z = 50 0 OUTPUT (a) Normal Load (Load 1) ALL INPUT PULSES Note 22. C also references C . OUT I/O Document Number: 38-06070 Rev. *L Description Input capacitance ...

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... This parameter is guaranteed by design, but it is not production tested. 25. Test conditions used are Load 2. Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV -167 -133 CY7C0851V / CY7C0851V / CY7C0851AV / CY7C0851AV / CY7C0853V / CY7C0852V / CY7C0852V / CY7C0853AV CY7C0852AV CY7C0852AV Min Max Min Max Min – ...

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... RSCNTINT flag reset time Notes 26. This parameter is guaranteed by design, but it is not production tested. 27. Test conditions used are Load 2. Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV -167 -133 CY7C0851V / CY7C0851V / CY7C0851AV / CY7C0851AV / CY7C0853V / CY7C0852V / CY7C0852V / CY7C0853AV CY7C0852AV CY7C0852AV Min Max Min ...

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... Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Document Number: 38-06070 Rev. *L Description Figure 7. JTAG Switching Waveform TMSS t TMSH t TDIS t TDIH t TDOX t TDOV CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 167/133/100 Min Max – 10 100 – 40 – 40 – 10 – 10 – 10 – 10 – – – ...

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... CL2 A A n+1 n+2 t CD2 CKLZ = HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and 1 following the next rising edge of the clock. IH with CNT/MSK = V IL CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV n n+1 t OHZ t OLZ ...

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... DATA IN DATA OUT Notes 33. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV device from this data sheet. ADDRESS = ADDRESS (B1) 34. ADS = CNTEN= B0 – LOW; MRST = CNTRST = CNT/MSK = HIGH. 35. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals. ...

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... OHZ READ WRITE t SAD t SCN t CD2 n COUNTER HOLD READ WITH COUNTER with CNT/MSK = V IL CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [39, 40, 41, 42 n+4 n CD2 CD2 Q n+1 READ [41] t HAD t HCN Q n+2 READ WITH COUNTER constantly loads the address on the rising edge of the CLK. ...

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... One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK. Document Number: 38-06070 Rev n n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD CYC2 t CH2 n+1 n+2 t CD2 Q n READ READ CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [43 n+2 n+3 n n+3 n+4 WRITE WITH COUNTER n ...

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... n+2 WRITE READ Figure 17. Disabled-to-Read to Disabled-to-Write CYC2 t CH2 n+1 n OHZ n+2 t CD2 Q n READ DISABLED CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV A A n+4 n CD2 Q Q n+1 READ READ WRITE A A n+3 n+4 Q WRITE READ READ Page n+3 n+3 ...

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... CL2 CLK t SAD ADS CNTEN t t SCN HCN ADDRESS COUNTER A INTERNAL n ADDRESS OE DATA OUT INCREMENT Document Number: 38-06070 Rev CH2 t HAD A n+1 Q n+1 NO OPERATION READ READBACK INCREMENT CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV n n+2 n+3 n+4 Q n+2 READ READ READ INCREMENT INCREMENT Page n+3 ...

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... Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value. Document Number: 38-06070 Rev. *L [44, 45, 46] Figure 19. Counter Reset CD2 t CKLZ WRITE READ READ ADDRESS 0 ADDRESS 1 ADDRESS 0 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV ...

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... the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines. Document Number: 38-06070 Rev CA2 CM2 n CD2 CKHZ CKLZ Q n INCREMENT in next clock cycle. CKLZ . CKHZ CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [47, 48, 49, 50 n+4 n+2 n n+1 n+2 n+3 Page ...

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... CCS CD2 CNTRST = MRST = CNT/MSK = HIGH. 1 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [51, 52, 53 violated, indeterminate data is Read out. CCS + t ) after the rising edge of R_Port's clock. CYC2 CD2 + t ) after the rising edge of R_Port's clock. CYC2 CD2 Page ...

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... R/W = CNTRST = MRST = HIGH 56. CNTINT is always driven. 57. CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value. 58. The mask register assumed to have the value of 1FFFFh. Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV [54, 55, 56, 57, 58] 1FFFE 1FFFF Last_Loaded t t ...

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... Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock. Document Number: 38-06070 Rev. *L [59, 60, 61, 62 SINT 3FFFF m m+1 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV A A n+2 n+3 t RINT A A m+3 m+4 Page ...

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... Care”, “H” = HIGH, “L” = LOW. Document Number: 38-06070 Rev. *L [66, 67, 64, 65] Outputs CE R/W DQ – High High OUT H X High Z CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Operation Deselected Deselected Write Read Outputs disabled Page ...

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... Speed Ordering Code (MHz) 167 CY7C0852V-167BBC CY7C0852AV-167AXC 133 CY7C0852AV-133AXC CY7C0852AV-133BBI CY7C0852AV-133AXI CY7C0852V-133BBC CY7C0852V-133BBI 64 K × 3.3 V Synchronous CY7C0851V/CY7C0851AV Dual-Port SRAM Speed Ordering Code (MHz) 167 CY7C0851V-167BBC CY7C0851AV-167BBXC 133 CY7C0851AV-133AXI CY7C0851AV-133BBI Document Number: 38-06070 Rev. *L http://www.cypress.com/products or contact your local sales representative. ...

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... Speed Grade: XXX = 100 MHz or 133 MHz or 167 MHz 3.3 V Depth 128 256 K Width × 36 Family Code Synchronous Port Dual Port Technology Code CMOS Marketing Code SRAM Company ID Cypress CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Page ...

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... Package Diagrams Figure 24. 172-ball FBGA (15 × 15 × 1.6 mm) BB172SD (For Single or Stacked Die) Package Outline, 51-85146 Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85146 *D Page ...

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... Package Diagrams (continued) Figure 25. 172-ball FBGA (15 × 15 × 1.25 mm) BB172 Package Outline, 51-85114 Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85114 *D Page ...

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... Package Diagrams (continued) Figure 26. 176-pin TQFP (24 × 24 × 1.4 mm) A176S Package Outline, 51-85132 Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV 51-85132 *B Page ...

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... SRAM static random access memory TCK test clock input TDI test data input TDO test data output TQFP thin quad flat pack Document Number: 38-06070 Rev. *L CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV Document Conventions Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µ ...

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... Document History Page Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV, FLEx36™ 3 128 K / 256 K × 36 Synchronous Dual-Port RAM Document Number: 38-06070 Submission Rev. ECN No. Date ** 127809 08/04/03 *A 210948 See ECN *B 216190 See ECN *C 231996 See ECN *D 238938 See ECN *E 329122 See ECN *F 389877 See ECN ...

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... Orig. of Description of Change Change RAME Updated Ordering Information information table). Updated Package Diagrams. ADMU Added information for parts CY7C0851V/CY7C0852V/CY7C0853V across the document. Added Contents. Updated Ordering Information ordering information table) and added Added Acronyms and Units of Updated as per new template. ADMU ...

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... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-06070 Rev. *L All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/USB Revised August 7, 2012 CY7C0851V/CY7C0851AV CY7C0852V/CY7C0852AV CY7C0853V/CY7C0853AV PSoC Solutions psoc.cypress.com/solutions PSoC 1 | ...