CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 8

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Master Reset
The FLEx36 family devices undergo a complete reset by taking
its
asynchronously to the clocks. The MRST initializes the internal
burst counters to zero, and the counter mask registers to all ones
(completely unmasked). The MRST also forces the Mailbox
Interrupt (INT) flags and the Counter Interrupt (CNTINT) flags
HIGH. The MRST must be performed on the FLEx36 family
devices after power up.
Mailbox Interrupts
The upper two memory locations may be used for message
passing and permit communications between ports.
shows
CY7C853V/CY7C0853AV. The highest memory location, 3FFFF
is the mailbox for the right port and 3FFFE is the mailbox for the
Table 1. Interrupt Operation Example
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)
Notes
Document Number: 38-06070 Rev. *L
Set right INT
Reset right INT
Set left INT
Reset left INT
5. 9 M device has 18 address bits, 4M device has 17 address bits, and 2M device has 16 address bits.
6. CE is internal signal. CE = LOW if CE
7. OE is “Don’t Care” for mailbox operation.
8. At least one of B0, B1, B2, or B3 must be LOW.
9. A16x is a NC for CY7C0851V/CY7C0851AV, therefore the Interrupt Addresses are FFFF and EFFF.
10. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
11. Counter operation and mask register operation is independent of chip enables.
CLK
can be deasserted after that. Data is out after the following CLK edge and is three-stated after the next CLK edge.
X
MRST input
the
MRST
L
R
flag
H
H
H
H
H
H
H
H
H
L
L
flag
Function
R
flag
interrupt
flag
CNT/MSK CNTRST
LOW.
H
H
H
H
H
X
L
L
L
L
operation
The
0
= LOW and CE
MRST input
X
H
H
H
H
H
H
H
L
L
for
[5, 6, 7, 8, 9]
R/W
X
X
H
L
both
1
ADS
L
= HIGH. For a single Read operation, CE only needs to be asserted once at the rising edge of the CLK and
X
X
H
H
X
H
L
L
L
L
can
CE
ports
L
X
X
L
CNTEN
Table 1
L
switch
Left Port
X
X
H
H
X
H
X
L
L
L
of
A
3FFFE
3FFFF
Master reset
Counter reset
Counter load
Counter readback Read out counter internal value on address
Counter increment Internally increment address counter value.
Counter hold
Mask reset
Mask load
Mask readback
Reserved
0L–17L
X
X
left port.
operation by the left port to address 3FFFF asserts INT
At least one byte has to be active for a Write to generate an
interrupt. A valid Read of the 3FFFF location by the right port
resets INT
a Read to reset the interrupt. When one port Writes to the other
port’s mailbox, the INT of the port that the mailbox belongs to is
asserted LOW. The INT is reset when the owner (port) of the
mailbox Reads the contents of the mailbox. The interrupt flag is
set in a flow-thru mode (that is it follows the clock edge of the
writing port). Also, the flag is reset in a flow-thru mode (that is it
follows the clock edge of the reading port).
Each port can read the other port’s mailbox without resetting the
interrupt. And each port can write to its own mailbox without
setting the interrupt. If an application does not require message
passing, INT pins should be left open.
Operation
Table 1
INT
R
X
X
H
L
HIGH. At least one byte has to be active in order for
L
shows that in order to set the INT
Reset address counter to all 0s and mask
register to all 1s.
Reset counter unmasked portion to all 0s.
Load counter with external address value
presented on address lines.
lines.
Constantly hold the address value for
multiple clock cycles.
Reset mask register to all 1s.
Load mask register with value presented on
the address lines.
Read out mask register value on address
lines.
Operation undefined
R/W
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
X
H
X
L
[10, 11]
R
CE
X
X
L
L
R
Description
Right Port
A
3FFFE
3FFFF
0R–17R
X
X
R
Page 8 of 39
flag, a Write
INT
R
H
X
X
L
LOW.
R