CY7C0851V CYPRESS [Cypress Semiconductor], CY7C0851V Datasheet - Page 37

• Manufacturer Part Number: CY7C0851V
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document History Page
Document Number: 38-06070 Rev. *L
Document Title: CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV/CY7C0853V/CY7C0853AV,
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM
Document Number: 38-06070
Rev.
*C
*D
*G
*H
*A
*B
*E
*F
**
ECN No.
2544945
127809
210948
216190
231996
238938
329122
389877
391597
Submission
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
08/04/03
07/29/08
Date
Change
Orig. of
DCON
YDT /
VKN /
AESA
WWZ
KGH
SPN
YDT
YDT
SPN
SPN
This data sheet has been extracted from another data sheet: The 2 M / 4 M /
9 M data sheet. The following changes have been made from the original as
pertains to this device:
Updated capacitance values
Updated “Read-to-Write-to-Read (OE Controlled)” waveform
Revised static discharge voltage
Corrected 0853 pins L3 and L12
Added discussion of Pause/Restart for JTAG boundary scan
Power up requirements added to Maximum Ratings information
Revised t
Updated I
Updated t
Separated out from the 4 M data sheet
Added 133 MHz Industrial device to Ordering Information table
Changed mailbox addresses from 1FFFE and 1FFFF to 3FFFE and 3FFFF.
Corrected Revision of Document. CMS does not reflect this rev change.
Updated
certain location while another port is reading that location.”).
Merged 0853 (9 M × 36) with 0852 (4 M × 36) and 0851 (2 M × 36), add 0850
(1 M × 36), to the data sheet.
Added
Added JTAG ID code for 1 M device.
Updated
the Bit Size ‘n’ of Bondary Scan).
Updated boundary scan section.
Updated function description for the merge and addition.
Updated
Updated Read-to-Write-to-Read timing diagram to reflect accurate bus
turnaround scheme.
Added I
Changed t
Changed t
Added figure Disabled-to-Read-to-Read-to-Read-to-Write
Added figure Disabled-to-Write-to-Read-to-Write-to-Read
Added figure Disabled-to-Read-to-Disabled-to-Write
Added figure Read-to-Readback-to-Read-to-Read (R/W = HIGH)
Updated Read-to-Write-to-Read timing diagram to correct the data out
schemes
Updated Disabled-to-Read-to-Read-to-Read-to-Write timing diagram to
correct the chip enable, data in, and data out schemes
Updated Disabled-to-Write-to-Read-to-Write-to-Read timing diagram to
correct the chip enable and output enable schemes
Updated Disabled-to-Read-to-Disabled-to-Write timing diagram to correct the
chip enable and output enable schemes
Updated counter reset section to reflect mirror register behavior
Updated
Updated in new template.
Product Selection
SB5
Scan Registers Sizes
Functional Description
Ordering Information
Ordering Information
CD2
CC
HA
RSCNTINT
RSF
, t
, t
numbers
HB
to 10 ns
OE
, t
, t
HD
OHZ
to 10 ns
for -100 speed
, t
CKHZ
Guide.
Description of Change
, t
(Updated Marketing part numbers).
(Updated part numbers).
(Added Note
CKLZ
(Removed “A particular port can write to a
CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
for the CY7C0853V to 4.7 ns
18
and referred the same note in
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