MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 6

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

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576Mb: x18, x36 RLDRAM 3
Features
Figure 51: READ-to-WRITE ............................................................................................................................ 88
Figure 52: Read Data Valid Window ................................................................................................................ 88
Figure 53: Bank Address-Controlled AUTO REFRESH Cycle ............................................................................. 89
Figure 54: Multibank AUTO REFRESH Cycle ................................................................................................... 89
Figure 55: READ Burst with ODT .................................................................................................................... 90
Figure 56: READ-NOP-READ with ODT .......................................................................................................... 91
Figure 57: Command Description in Multiplexed Address Mode ..................................................................... 92
Figure 58: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 93
Figure 59: MR0 Definition for Multiplexed Address Mode ................................................................................ 94
Figure 60: MR1 Definition for Multiplexed Address Mode ................................................................................ 95
Figure 61: MR2 Definition for Multiplexed Address Mode ................................................................................ 96
Figure 62: Bank Address-Controlled AUTO REFRESH Operation with Multiplexed Addressing .......................... 97
Figure 63: Multibank AUTO REFRESH Operation with Multiplexed Addressing ................................................ 97
Figure 64: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 98
Figure 65: WRITE-to-READ with Multiplexed Addressing ................................................................................ 99
Figure 66: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 99
Figure 67: READ-to-WRITE with Multiplexed Addressing ............................................................................... 100
Figure 68: TAP Controller State Diagram ........................................................................................................ 104
Figure 69: TAP Controller Functional Block Diagram ..................................................................................... 104
Figure 70: JTAG Operation - Loading Instruction Code and Shifting Out Data ................................................. 107
Figure 71: TAP Timing .................................................................................................................................. 108
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576mb_rldram3.pdf – Rev. B 1/12 EN
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