MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 74

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

WRITE Protocol
WRITE Command
Figure 37: WRITE Command
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
Single or multibank WRITE operation is programmed with bits MR2[4:3]. The purpose
of multibank WRITE operation is to reduce the effective
When dual- or quad-bank WRITE protocol is selected, identical data is written to two or
four banks, respectively. With the same data stored in multiple banks on the RLDRAM,
the memory controller can select the appropriate bank to READ the data from and min-
imize
in Multibank WRITE (page 75).
Write accesses are initiated with a WRITE command. The address needs to be provided
concurrent with the WRITE command.
During WRITE commands, data will be registered at both edges of DK, according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) de-
termined by the data latency bits within MR0. The first valid data is registered at the first
rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming
met). Depending on the amount of input timing skew, an additional NOP command
might be necessary between WRITE and READ commands to avoid external data bus
contention (see Figure 44 (page 83)).
Setup and hold times for incoming DQ relative to the DK edges are specified as
t
Address
Address
DH. The input data is masked if the corresponding DM signal is HIGH.
WE#
REF#
Bank
CK#
CS#
CK
t
RC delay. Detailed information on the multibank WRITE protocol can be found
Don’t Care
BA
A
74
Micron Technology, Inc. reserves the right to change products or specifications without notice.
576Mb: x18, x36 RLDRAM 3
t
RC during READ commands.
© 2011 Micron Technology, Inc. All rights reserved.
WRITE Command
t
t
DS and
RC is