MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 75

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Multibank WRITE
READ Command
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
All the information provided above in the WRITE section is applicable to a multibank
WRITE operation as well. Either two or four banks can be simultaneously written to
when the appropriate MR2[4:3] mode register bits are selected.
If a dual-bank WRITE has been selected through the mode register, both banks x and x
+8 will be written to simultaneously with identical data provided during the WRITE
command. For example, when a dual-bank WRITE has been loaded and the bank ad-
dress for Bank 1 has been provided during the WRITE command, Bank 9 will also be
written to at the same time. When a dual-bank WRITE command is issued, only bank
address bits BA[2:0] are valid and BA3 is considered a “Don’t Care.”
The same methodology is used if the quad-bank WRITE has been selected through the
mode register. Under these conditions, when a WRITE command is issued to Bank x,
the data provided on the DQs will be issued to banks x, x+4, x+8, and x+12. When a
quad-bank WRITE command is issued, only bank address bits BA[1:0] are valid and
BA[3:2] are considered “Don’t Care.”
The timing parameter
commands. This parameter limits the number of active banks at 16 within an 8ns win-
dow. The
used. This specification requires two clock cycles between any bank command (READ,
WRITE, or AREF) to a quad-bank WRITE or a quad-bank WRITE to any bank command.
The data bus efficiency is not compromised if BL4 or BL8 is being utilized.
Read accesses are initiated with a READ command (see the figure below). Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QK signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal(s), QVLD,
transitions from LOW to HIGH. QVLD is also edge-aligned with the QK signals.
The skew between QK and the crossing point of CK is specified as
skew between a QK pair and the last valid data edge generated at the DQ signals in the
associated byte group, such as DQ[7:0] and QK0.
and is not cumulative over time. For the x36 device, the
tions define the relationship between the DQs and QK signals within specific data word
groupings.
DQ[8:0].
DQ[17:9].
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. The QK clocks are free-running and will continue to cycle after the read burst is
complete. Back-to-back READ commands are possible, producing a continuous flow of
output data.
Any READ burst may be followed by a subsequent WRITE command. Some systems
having long line lengths or severe skews may need an additional idle cycle inserted be-
tween READ and WRITE commands to prevent data bus contention.
t
t
QKQ13 defines the skew between QK1 and DQ[35:17] and between QK3 and
MMD specification must also be followed if the quad-bank WRITE is being
t
QKQ02 defines the skew between QK0 and DQ[26:18] and between QK2 and
t
SAW must be adhered to when operating with multibank WRITE
75
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
QKQx is derived at each QK clock edge
576Mb: x18, x36 RLDRAM 3
t
QKQ02 and
© 2011 Micron Technology, Inc. All rights reserved.
READ Command
t
CKQK.
t
QKQ13 specifica-
t
QKQx is the