MT44K16M36 MICRON [Micron Technology], MT44K16M36 Datasheet - Page 95

• Manufacturer Part Number: MT44K16M36
• Description: 576Mb: x18, x36 RLDRAM 3
• Manufacturer: MICRON [Micron Technology]

Figure 60: MR1 Definition for Multiplexed Address Mode
PDF: 09005aef84003617
576mb_rldram3.pdf – Rev. B 1/12 EN
M19
0
0
1
1
M18
0
1
0
1
Mode Register Definition
Mode Register 0 (MR0)
Mode Register 1 (MR1)
Mode Register 2 (MR2)
Notes:
Reserved
1. BA2, BA3, and all address balls corresponding to reserved bits must be held LOW during
2. BL8 not available in x36.
M8
0
1
the MRS command.
Bank Address Control
M10
0
0
1
1
AREF Protocol
Multibank
M9
0
1
0
1
BA3
0
21
1
Burst Length
20
0
BA2
Reserved
1
Ax
Ay
19
2
4
8
MRS
BA1
A18.......A13
A18.......A13
18
BA0
Reserved
17-11
M7
0
1
A10
ZQ Calibration Enable
10
Disabled - Default
BL
M6
0
1
2
A9 A8
95
9
ZQ Calibration Selection
Enable
Ref
Short ZQ Calibration
Long ZQ Calibration
8
ZQe
A9
M5
7
0
1
ZQ
A8
6
DLL Reset
DLL
Yes
5
No
A5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4
A4
ODT
3
A3
M4
A4
2
0
0
0
0
1
1
1
1
Drive
M3
A3
1
0
0
1
1
0
0
1
1
576Mb: x18, x36 RLDRAM 3
Multiplexed Address Mode
0
M2
A0
0
1
0
1
0
1
0
1
Mode Register (Mx)
RZQ/2 (120W)
Address Bus
RZQ/6 (40W)
RZQ/4 (60W)
Reserved
Reserved
Reserved
Reserved
ODT
Off
© 2011 Micron Technology, Inc. All rights reserved.
M1
0
0
1
1
M0
0
1
0
1
Output Drive
RZQ/6 (40W)
RZQ/4 (60W)
Reserved
Reserved