MC14536 ONSEMI [ON Semiconductor], MC14536 Datasheet - Page 5

• Manufacturer Part Number: MC14536
• Description: Programmable Timer
• Manufacturer: ONSEMI [ON Semiconductor]

INPUTS
Decode Out to a high level. This is accomplished by setting
an output conditioning latch to a high level while at the same
time resetting the 24 flip–flop stages. After Set goes low
(inactive), the occurrence of the first negative clock
transition on IN
counter’s flip–flop stages begin counting on the second
negative clock transition of IN
on–chip RC oscillator is disabled. This allows for very
low–power standby operation.
forces Decode Out to a low level; all 24 flip–flop stages are
also reset to a low level. Like the Set input, Reset disables
the on–chip RC oscillator for standby operation.
the negative–going edge of this input. IN
external clock input or used in conjunction with OUT
OUT
used, both OUT
used to drive 1 LSTTL or several CMOS loads.
8 flip–flop stages to be bypassed. This device essentially
becomes a 16–stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
start–up time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN
SET (Pin 1) — A high on Set asynchronously forces
RESET (Pin 2) — A high on Reset asynchronously
IN
8–BYPASS (Pin 6) — A high on this input causes the first
CLOCK INHIBIT (Pin 7) — A high on this input
1
2
(Pin 3) — The device’s internal counters advance on
to form an RC oscillator. When an external clock is
1
1
and OUT
causes Decode Out to go low. The
2
may be left unconnected or
1
. When Set is high, the
1
may be used as an
1
.
PIN DESCRIPTIONS
http://onsemi.com
1
MC14536B
and
5
the RC oscillator which allows for very low–power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
on–chip monostable multivibrator. If the Mono–In input is
connected to V
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono–In and V
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
V
operation the resistor value should be limited to the range of
5 k to 100 k and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 3, 4, 5, and 10).
flip–flop stage to be connected to Decode Out. (See the truth
tables.)
OUTPUTS
with IN
buffered and may be used for 2
external clock.
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
stages into three 8–stage sections to facilitate a fast test
sequence. The test mode is enabled when 8–Bypass, Set and
Reset are at a high level. (See Figure 8.)
SS
OSC INHIBIT (Pin 14) — A high level on this pin stops
MONO–IN (Pin 15) — Used as the timing pin for the
A, B, C, D (Pins 9, 10, 11, 12) — These inputs select the
OUT
DECODE OUT (Pin 13) — Output function depends on
The test mode configuration divides the 24 flip–flop
, the pulse width range may be extended. For reliable
1
1
, OUT
to form an RC oscillator. These outputs are
2
SS
(Pin 4, 5) — Outputs used in conjunction
, the monostable circuit is disabled, and
DD
. This resistor and the device’s
0
frequency division of an