CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 20

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated
to USB FIFOs. The memory requirements for the USB endpoints are described in Section 19.2. Example assembly instructions
to do this with two device addresses (FIFOs begin at 0xD8) are shown below:
5.6
The CY7C66013C and CY7C66113C microcontrollers support three addressing modes for instructions that require data
operands: data, direct, and indexed.
5.6.1
“Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the
instruction that loads A with the constant 0xD8:
This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction is the constant “0xD8”. A constant may be referred to by name if a prior “EQU”
statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:
5.6.2
“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the
variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address
location 0x10:
Normally, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler
source code. As an example, the following code is equivalent to the example shown above:
5.6.3
“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is
the sum of a constant encoded in the instruction and the contents of the “X” register. Normally, the constant is the “base” address
of an array of data and the X register contains an index that indicates which element of the array is actually addressed:
This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.
6.0
The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to
these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than
• MOV A, 0D8h.
• DSPINIT: EQU 0D8h
• MOV A, DSPINIT.
• MOV A, [10h].
• buttons: EQU 10h
• MOV A, [buttons].
• array: EQU 10h
• MOV X, 3
• MOV A, [X+array].
MOV A,20h; Move 20 hex into Accumulator (must be D8h or less)
SWAP A,DSP; swap accumulator value into DSP register.
Address Modes
Data (Immediate)
Direct
Indexed
Clocking
XTALOUT
(pin 1)
XTALIN
(pin 2)
Figure 6-1. Clock Oscillator On-Chip Circuit
30 pF
30 pF
To Internal PLL
CY7C66013C
CY7C66113C
Page 20 of 61
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