CY7C66113C-XC CYPRESS [Cypress Semiconductor], CY7C66113C-XC Datasheet - Page 29

• Manufacturer Part Number: CY7C66113C-XC
• Description: Full-Speed USB (12 Mbps) Peripheral Controller with Integrated Hub
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-08024 Rev. *B
The I
Table 13-1. I
Bit 7: MSTR Mode
Bit 6: Continue/Busy
Bit 5: Xmit Mode
Bit 4: ACK
Bit 3: Addr
Bit 2: ARB Lost/Restart
Bit
0
1
2
3
4
5
6
7
2
Setting this bit to 1 causes the I
transmitting the first data byte from the data register (this typically holds the target address and R/W bit). Subsequent bytes
are initiated by setting the Continue bit, as described below.
Clearing this bit (set to 0) causes the GPIO pins to operate normally
In master mode, the I
transmit or receive state. The I
event of a loss of arbitration, this MSTR bit is cleared, the ARB Lost bit is set, and an interrupt is generated by the
microcontroller. If the chip is the target of an external master that wins arbitration, then the interrupt is held off until the
transaction from the external master is completed.
When MSTR Mode is cleared from 1 to 0 by a firmware write, an I
This bit is written by the firmware to indicate that the firmware is ready for the next byte transaction to begin. In other words,
the bit has responded to an interrupt request and has completed the required update or read of the data register. During a
read this bit indicates if the hardware is busy and is locking out additional writes to the I
locking allows the hardware to complete certain operations that may require an extended period of time. Following an I
interrupt, the I
firmware to make one control register write without the need to check the Busy bit.
This bit is set by firmware to enter transmit mode and perform a data transmit in master or slave mode. Clearing this bit
sets the part in receive mode. Firmware generally determines the value of this bit from the R/W bit associated with the I
address packet. The Xmit Mode bit state is ignored when initially writing the MSTR Mode or the Restart bits, as these cases
always cause transmit mode for the first byte.
This bit is set or cleared by firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I
time. During transmits (Xmit Mode = 1), this bit should be cleared.
This bit is set by the I
The Addr bit is cleared when the firmware sets the Continue bit. This bit allows the firmware to recognize when the master
has lost arbitration, and in slave mode it allows the firmware to recognize that a start or restart has occurred.
This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the
Continue and MSTR Mode bits) to perform an I
to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware
during the restart sequence.
C Status and Control register bits are defined in Table 13-1, with a more detailed description following.
I
Received Stop
ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Addr
ACK
Xmit Mode
Continue/Busy
MSTR Mode
2
C Enable
2
2
C Status and Control Register Bit Definitions
C-compatible bus. Writing a 1 to this bit generates an ACK (SDA LOW) on the I
Name
2
C-compatible block does not return to the Busy state until firmware sets the Continue bit. This allows the
2
2
C-compatible block generates the clock (SCK), and drives the data line as required depending on
C-compatible block during the first byte of a slave receive transaction, after an I
When set to ‘1’, the I
normally.
Reads 1 only in slave receive mode, when I
last transaction).
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
Write 1 to indicate ready for next transaction.
Reads 1 when I
Clearing from 1 to 0 generates Stop bit.
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
2
C-compatible block performs any required arbitration and clock synchronization. IN the
2
C-compatible block to initiate a master mode transaction by sending a start bit and
2
C-compatible block is busy with a transaction, 0 when transaction is complete.
2
C-compatible function is enabled. When cleared, I
2
C restart sequence. The I
2
Description
C Stop bit is generated.
2
C Stop bit detected (unless firmware did not ACK the
2
C target address for the restart must be written
2
C Status and Control register. This
2
C-compatible bus at the ACK bit
2
C GPIO pins operate
CY7C66013C
CY7C66113C
2
C start or restart.
Page 29 of 61
2
2
C
C
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